hi EVERYBODY As a part of my project i wanted to transmit encoded speech data though one board as a transmitter to other board. i used 32k...

hi EVERYBODY As a part of my project i wanted to transmit encoded speech data though one board as a transmitter to other board. i used 32k sampling frequency at the transmitter. at the receiver side i uysed pll for phase lock and synchrouns bits for frame synchronization.andgiven output to speakers iam hearing the speech with noise for some duration and some time only noise. i tried in all...

Hello. I'm working on c6711 and I have some doubts about clocks rate. I use audio example from Code Composer. Because I want to implement a MELP...

Hello. I'm working on c6711 and I have some doubts about clocks rate. I use audio example from Code Composer. Because I want to implement a MELP vocoder, I set frame length in pipelines to be 180 words (to fit the MELP frame). For 8kHz sampling rate it makes one frame filled every 22,5 ms and then software interruption occurs. c6711 works on 150MHz clock rate, so in 22,5 ms period I should get...

Hi, 1-As I know in SPI mode there is not the feature to program FPER in McBSP. I want to read 16-bit samples every 125us in SPI mode. (it is...

Hi, 1-As I know in SPI mode there is not the feature to program FPER in McBSP. I want to read 16-bit samples every 125us in SPI mode. (it is compulsory). I want to use DMA and not add any checking or time consuming code to my project. 2- If my cpu internal clk is 120 MHz and the CLKGDV field of my SRGR is 8 bits, how can I use mcbsp(in SPI mode) with internal clk source and with 100KHz...

Hi. Last time I asked about the reason of wrong number of ticks in one interruption period. I spent a lot of time checking codec and DSP and I...

Hi. Last time I asked about the reason of wrong number of ticks in one interruption period. I spent a lot of time checking codec and DSP and I had the following results: -the sampling frequency in codec is 8kHz and it's mono for sure! -the sync signal between codec and DSP is also 8kHz, one 16-bit sample is sent or recieved every 125us -however, the DSP puts one sample into PIP frame every 250...

Hello All, I am new to DSP programming and am experiencing some difficulties implementing filters on a fixed point DSP (TMS320C6416). To...

Hello All, I am new to DSP programming and am experiencing some difficulties implementing filters on a fixed point DSP (TMS320C6416). To keep it simple, I started trying to implement a single pole low pass filter with a corner frequency of 500 Hz while sampling at 96kHz. I have obtained the quantized filter coefficients using Matlab's fdatool. I have then written down type 1 direct fo...

Ramaraju- > According to system requirement, DSP has to acquire sampled data around 5 seconds @ > 51KHz sampling fervency. > To implement...

Ramaraju- > According to system requirement, DSP has to acquire sampled data around 5 seconds @ > 51KHz sampling fervency. > To implement real time filter, we configured 2 ping-pong buffers. While McBSP fills > one buffer, another buffer can be used for processing (which was already filled). > There will be considerable time gap between two fills, which is sufficient to > execute filter algo

Hi Guys, I have computed FFT of 1 KHz sine wave with 1 Vp_p using C6713 DSK, to be sure that FFT algorithm is working fine, I want to verify my...

Hi Guys, I have computed FFT of 1 KHz sine wave with 1 Vp_p using C6713 DSK, to be sure that FFT algorithm is working fine, I want to verify my result. Can you please tell me how can I do this. Sampling frequency used is 8KHz and no. of FFT points are 256. Waiting for your quick response. BR, BS

Hi C6x Group members, I'm trying testing the MIPS of C6713 on DSK6713. I have a simple loop-back program to get an audio sample from A/D then...

Hi C6x Group members, I'm trying testing the MIPS of C6713 on DSK6713. I have a simple loop-back program to get an audio sample from A/D then output to D/A. There is some delay between input and output so I can figure out the MIPS. Why can I only execute maximum 3000 times of (a+b) for this delay? So for 8kHz sampling rate, the MIPS is only 3000*8000=24MIPS. Anything wrong with my program? ...

Dear everybody, I want to plot Eb/N0 vs BER bpsk demodulation in Matlab. I am using BPSK modulated signal @ carrier...

Dear everybody, I want to plot Eb/N0 vs BER bpsk demodulation in Matlab. I am using BPSK modulated signal @ carrier frequencey 8KHz, data rate 1KHz. Sampling rate is set to 96000Hz. I have tried to use 'awgn function' for adding noise. This signal accepts Signal to noise ratio (SNR)in parameters. In order to convert into Eb/N0 for BPSK signal. I have used following relat...

Manimaran, I'm not familiar with the 'rapid IO' process... For 28 channels, I would have the fpga do all the sampling and have the fpga...

Manimaran, I'm not familiar with the 'rapid IO' process... For 28 channels, I would have the fpga do all the sampling and have the fpga present the data to the DSP. I'm not sure if the selected DSP has an external interface,? if it does, then the DSP can read the finished data as a regular memory access. however, If the selected DSP does not have an external interface, then I would use t...

hi friends As a part of my project i wanted to transmit encoded speech data though one board as a transmitter to other board. i used 32k...

hi friends As a part of my project i wanted to transmit encoded speech data though one board as a transmitter to other board. i used 32k sampling frequency at the transmitter. at the receiver side i uysed pll for phase lock and synchrouns bits for frame synchronization.andgiven output to speakers iam hearing the speech with noise for some duration and some time only noise. i tried in all th...

This is a basic program from Rulph Chassing book //Sine8_LED.c Sine generation with DIP switch control #include "dsk6713_aic23.h" //support...

This is a basic program from Rulph Chassing book //Sine8_LED.c Sine generation with DIP switch control #include "dsk6713_aic23.h" //support file for codec,DSK Uint32 fs = DSK6713_AIC23_FREQ_8KHZ; //set sampling rate short loop = 0; //table index short gain = 10; //gain factor short sine_table[8]={0,707,1000,707,0,-707,-1000,-707};//sine values void main() { comm_poll(); //init DSK, ...

Hello, Im planning a 6713DSK based design and am thinking of using timer1 to create a periodic ISR to handle continuous sampling an of ADC.(Im...

Hello, Im planning a 6713DSK based design and am thinking of using timer1 to create a periodic ISR to handle continuous sampling an of ADC.(Im still very new with this DSK, and so havent tried it out myself) Assuming I keep the ISR short (ie: read the ADC, toggle a GPIO, output to a DAC, some housekeeping), can someone give me a rough estimate of how fast I can expect to be able to sample ? ...

Hi, sorry for the repost i forgot to paste the error message. I'm usng ccs 2.2. Can anyone help me please. Thank you. #include...

Hi, sorry for the repost i forgot to paste the error message. I'm usng ccs 2.2. Can anyone help me please. Thank you. #include "rtdx_vbloopcfg.h" #include "dsk6416_aic23.h" //codec-DSK support file #include #include "target.h" Uint32 fs=DSK6416_AIC23_FREQ_48KHZ; //set sampling rate int gain = 1; RTDX_CreateInputChannel(control_channel); interrupt void c_int11()

Does anyone have any sample code to drive the AIC23 on the TMS320C6455DSK, the code provided in the POST does not seem to work as expected. After...

Does anyone have any sample code to drive the AIC23 on the TMS320C6455DSK, the code provided in the POST does not seem to work as expected. After modifying the audio loop test to only use the AIC23_read32() function (and removing the write32() function) the output in the sampling buffer is incorrect. I used a 1kHz sine wave as input to the AIC23, but in the buffer it did not show the sine wave...

I still haven't resolved my problem with the AIC23 on the TMS320C6455EVM. After viewing the different options available, I tried to use the Data...

I still haven't resolved my problem with the AIC23 on the TMS320C6455EVM. After viewing the different options available, I tried to use the Data Converter Support by selecting "Codec, Serial interface -> 18-24 bit -> TLV320AIC23: 96kHz, Audio, Stereo -> Aic23_4" and then setting the AIC23 mode to USB and selecting 48/48 kHz sampling rates and insured that the Line Input is activated. In the DSP

hi i made be tired some dear friends such as "jeff" because my question is a few information about my question!! this very unknown i use...

hi i made be tired some dear friends such as "jeff" because my question is a few information about my question!! this very unknown i use figure 2 (http://ee.iust.ac.ir/81412497/dspc6x_interface.htm) and my a2d sampling rate is 15 Mbps and 12 bit sample i am in pcb design with Altium 2004 DXP my question is in pcb design which special notes must be done (in addition typical notes : ...

I have not used dm642 before. But want to know about its video ports. Few Q's are below. Can someone help me in them... Can it be used for...

I have not used dm642 before. But want to know about its video ports. Few Q's are below. Can someone help me in them... Can it be used for video signal i\p as well o\p? i think it is for dual purpose! What is signal i\p and o\p format(RGB\YCbCr sampling rate etc)? Can we set desired frame size and frame rate? Is this operation of i\p and o\p can be through 2 ports on same dsk in parall...

Hi, I will appreciate if some one help me grasping some knowledge of interfacing ADC with DSP. I am intending to use OMAP-L138 Experimenter Kit...

Hi, I will appreciate if some one help me grasping some knowledge of interfacing ADC with DSP. I am intending to use OMAP-L138 Experimenter Kit for frequency domain analysis of real signal with maximum frequency 2 MHz. I need to select an ADC with maximum sampling frequency 10 MHz. I know there are several ADCs with different interfaces, which are available in the market. I have low knowledge o...

What means 3rd order architecture and dBA short? It's from codec AIC23's manual: "The ADC sigma-delta modulator features third-order multibit...

What means 3rd order architecture and dBA short? It's from codec AIC23's manual: "The ADC sigma-delta modulator features third-order multibit architecture with up to 90-dBA signal-to-noise ratio (SNR) at audio sampling rates up to 96 kHz, enabling high-fidelity audio recording in a compact, power-saving design. The DAC sigma-delta modulator features a second-order multibit architecture wi...