Summary

Rick Lyons presents a practical technique to substantially reduce the number of multiplies per input sample in conventional IIR lowpass and highpass digital filters. The paper explains the structural modifications, implementation considerations, and trade-offs so readers can adopt the approach in real-time and resource-constrained systems.

Key Takeaways

• Apply a coefficient-sharing/structure-modification method to lower per-sample multiply counts for IIR lowpass and highpass filters.
• Quantify expected compute savings and trade-offs (CPU cycles, memory, and latency) for common filter orders and sampling rates.
• Preserve filter frequency response and stability while implementing the reduced-multiply structure, including guidance on coefficient scaling and fixed-point care.
• Benchmark and integrate the method into real-time DSP or embedded implementations and compare it to standard direct-form and biquad realizations.

Who Should Read This

DSP engineers and developers implementing IIR filters in real-time or resource-constrained systems who want to reduce multiply cost without sacrificing filter performance.

Still RelevantIntermediate

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