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Started by I believe there are two equally important events we can experience in our DSP work. The first kind of important event is when we examine the results of our designed...
Started by I am looking at the pre-release Analog Devices AD9084 -- APOLLO MxFE. This has 4TX and 4Rx and ADC/DAC at 20/28 Gsps. There is also a less capable but similar...
Started by Good day all,I am having some problems with my TMS320C6713 DSK Kit. I have the book "Digital Signal Processing and Applications with TMS320C6713" by Chassaing and...
Are all signal processing algorithms in communication and control going to be replaced by machine learning and AI.Is it still worth to look in to conventional signal...
Moving the notches of a Moving Average Filter
Started by 2 months ago●9 replies●latest reply 2 months ago●196 viewsHi!Is there a way of slightly moving all the notches of a recursive MAV filter without changing the sampling period?The order of my filter is 16, and changing it...
Generate 2KHz damped sine wave using DAC
Started by 2 months ago●19 replies●latest reply 2 months ago●195 viewsI would like to generate a 2KHz damped sine wave from the DAC of my microcontroller (STM32). How to impose the exponential decay lasting for 1second on the 2KHz...
Variable IIR-Filter Coefficient calculation in frequency domain
Started by 5 months ago●6 replies●latest reply 2 months ago●307 viewsHello,Currently im evaluating the usefulness of frequency domain filtering in FPGA for one of our projects. Im stuck with a problem that my limited knowledge of...
Error in frequency estimation for low frequencies
Started by 3 months ago●28 replies●latest reply 2 months ago●219 viewsHello everyoneWe want to use a chirp z-transform to determine the frequency of a signal more accurately. It works quite well, but we see that the accuracy is much...
Maximally Decimated Polyphase Channelizer Help
Started by 2 months ago●3 replies●latest reply 2 months ago●174 views#python #Polyphase #ChannelizerI'm hoping someone can help me with this maximally decimated polyphase channelizer I've coded up. This is based on the fitler_ten_a...
How to design cic digital filter for sigma delta adc
Started by 3 months ago●7 replies●latest reply 2 months ago●207 viewsMy SD ADC modulator has a sampling frequency of 1.024 MHz, an input bandwidth of 1 kHz, an oversampling ratio of 512, a single-loop second-order structure, and a...
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