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Hi All,If this isn't the right place for this I apologize, I've tried a couple of other forums as well and I'm striking out.I'm trying to write Hoagenaur's equations...
So this is a curious one. I am continuing investigating #CIC filters now that I have run @Rick Lyons tests and proven to myself that they are now correctly implemented....
Rick Lyons posted an informative post about testing the implementation of your #CIC decimation filters here: Two Easy Ways to Test Multistage CIC Decimation Filters...
I'm implementing a #CIC decimation filter. I'm doing it on an microprocessor rather than in an FPGA and that means I don't "easily" get variable bit width registers....
Understanding cascaded integrators
Started by 5 years ago●2 replies●latest reply 5 years ago●287 viewsHi All,I am working my way though the design and implementation of a #CIC filter to process the output of a PDM waveform (coming from a MEMS microphone). I know...
Hi all,I need some help to design a CIC Filter. The #CIC Filter I am trying to design has following properties:Decimation factor R= 10Differential Delay M= 2Stages...
CIC Filter "zero-crossing" Distortion
Started by 7 years ago●7 replies●latest reply 7 years ago●299 views#CIC@Rick LyonsI am trying to design a decimation filter with decimation rate at 100 and bandwidth around 1Hz to 100Hz. Of course the exact bandwidth will be finalized...
Can we paralleize the integrator stage of CIC?
Started by 8 years ago●13 replies●latest reply 8 years ago●695 viewsHi,Since, the integrator stage of #CIC operates at higher frequency compared to differentiator, it becomes critical for timing in a high-speed design. Is there a...
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