Fixed-Point Analysis of a PDM Modulator with GNU Octave's FXP Package
A thorough analysis of a first order PDM loop in fixed-point. The FXP package is valuable asset to analysis fixed-point impact on discrete systems at early stage of the design prior implementation.
Spline interpolation
Markus Nentwig provides a cookbook for segmented cubic spline interpolation that turns scattered or noisy data into efficient fixed-point functions. The article shows how to build third-order polynomial segments with explicit value and slope control via basis functions, solve scaling factors by least-squares in Octave/Matlab, and export coefficients for Verilog RTL evaluation using the Horner scheme and practical fixed-point tips.
Signed serial-/parallel multiplication
Struggling with costly wide adders for signed multiplication on FPGAs? Markus Nentwig unpacks a neat bit-level trick that turns two's-complement signed-signed multiplication into a serial-parallel routine using only a one-bit wider adder. Learn how flipping sign bits and a small, controlled constant cancel lets you avoid full sign-extension, and get a parametrized Verilog RTL plus synthesis notes to try it yourself.
DSP Algorithm Implementation: A Comprehensive Approach
This post lays out a practical pathway for taking DSP algorithms from high level simulation to production hardware, comparing GPP, DSP, FPGA and ASIC platforms. It presents a stepwise methodology starting with nested loop programs, then exposing parallelism with data flow graphs, using SystemC transaction level modeling to bridge to Verilog or VHDL, and explains why that flow speeds design and simulation.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
Fixed-Point Analysis of a PDM Modulator with GNU Octave's FXP Package
A thorough analysis of a first order PDM loop in fixed-point. The FXP package is valuable asset to analysis fixed-point impact on discrete systems at early stage of the design prior implementation.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
Spline interpolation
Markus Nentwig provides a cookbook for segmented cubic spline interpolation that turns scattered or noisy data into efficient fixed-point functions. The article shows how to build third-order polynomial segments with explicit value and slope control via basis functions, solve scaling factors by least-squares in Octave/Matlab, and export coefficients for Verilog RTL evaluation using the Horner scheme and practical fixed-point tips.
DSP Algorithm Implementation: A Comprehensive Approach
This post lays out a practical pathway for taking DSP algorithms from high level simulation to production hardware, comparing GPP, DSP, FPGA and ASIC platforms. It presents a stepwise methodology starting with nested loop programs, then exposing parallelism with data flow graphs, using SystemC transaction level modeling to bridge to Verilog or VHDL, and explains why that flow speeds design and simulation.
Signed serial-/parallel multiplication
Struggling with costly wide adders for signed multiplication on FPGAs? Markus Nentwig unpacks a neat bit-level trick that turns two's-complement signed-signed multiplication into a serial-parallel routine using only a one-bit wider adder. Learn how flipping sign bits and a small, controlled constant cancel lets you avoid full sign-extension, and get a parametrized Verilog RTL plus synthesis notes to try it yourself.
Signed serial-/parallel multiplication
Struggling with costly wide adders for signed multiplication on FPGAs? Markus Nentwig unpacks a neat bit-level trick that turns two's-complement signed-signed multiplication into a serial-parallel routine using only a one-bit wider adder. Learn how flipping sign bits and a small, controlled constant cancel lets you avoid full sign-extension, and get a parametrized Verilog RTL plus synthesis notes to try it yourself.
Spline interpolation
Markus Nentwig provides a cookbook for segmented cubic spline interpolation that turns scattered or noisy data into efficient fixed-point functions. The article shows how to build third-order polynomial segments with explicit value and slope control via basis functions, solve scaling factors by least-squares in Octave/Matlab, and export coefficients for Verilog RTL evaluation using the Horner scheme and practical fixed-point tips.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
DSP Algorithm Implementation: A Comprehensive Approach
This post lays out a practical pathway for taking DSP algorithms from high level simulation to production hardware, comparing GPP, DSP, FPGA and ASIC platforms. It presents a stepwise methodology starting with nested loop programs, then exposing parallelism with data flow graphs, using SystemC transaction level modeling to bridge to Verilog or VHDL, and explains why that flow speeds design and simulation.
Fixed-Point Analysis of a PDM Modulator with GNU Octave's FXP Package
A thorough analysis of a first order PDM loop in fixed-point. The FXP package is valuable asset to analysis fixed-point impact on discrete systems at early stage of the design prior implementation.
