Simple Concepts Explained: Fixed-Point
Fixed-point is the bridge between real-world values and integer arithmetic, and this post makes that bridge tangible with a hands-on ADC-to-gain example. It walks through mapping voltages to Q-format integers, choosing gain resolution in bits, and how multiplication adds bit growth and produces quantization error. Read it to build intuition for practical fixed-point choices when implementing DSP on FPGA or ASIC.
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Feedback Controllers - Making Hardware with Firmware. Part 8. Control Loop Test-bed
Built around modest FPGA hardware, this post presents a practical test-bed for evaluating high-speed, low-latency feedback controllers. It covers ADC/DAC specifications, basic and arbitrary test signals, and an IFFT-based generator that can produce thousands of simultaneous tones for rapid Bode, phase, and latency measurements. The article also compares two IFFT strategies, explains turbo sampling, and shows open- and closed-loop test configurations.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
Feedback Controllers - Making Hardware with Firmware. Part 6. Self-Calibration Related.
Self-calibration is the missing piece that turns this mixed-signal hardware from a prototype into a usable instrument. In this installment, the author lays out how the board will measure itself, generate reference signals, and verify ADC and DAC behavior before the low-latency control firmware is built. The result is a practical framework for evaluation, production test, and routine self-test.
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This installment digs into practical FPGA choices and board-level issues for a low-latency, floating-point feedback controller. It compares a Cyclone V implementation against an older SHARC-based design, quantifies the tradeoff between raw DSP resources and cycle latency, and calls out Gotchas found on the BeMicro CV A9 evaluation card. Engineers get concrete prompts for where to optimize: clocking, DSP-block use, I/O standards, and algorithm partitioning.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
This installment follows the hardware from concept to first power-up for a low-latency feedback controller and arbitrary circuit emulator. It walks through the practical engineering steps, from requirements, block diagrams, and issue tracking to component selection, simulation, PCB planning, purchasing, and staged bring-up. The result is a realistic look at how careful due diligence and a few trade-offs turned a research idea into working evaluation hardware.
Feedback Controllers - Making Hardware with Firmware. Part 3. Sampled Data Aspects
This article digs into practical sampled-data issues you must address when building feedback controllers for circuit emulation. It highlights a common MATLAB versus Simulink discrepancy caused by DAC holding, explains why FOH (ramp-invariant) c2d conversion matters, and surveys latency, bit depth, filter and precision trade-offs. It also lists candidate ADCs, DACs and FPGAs used in a real evaluation platform to guide hardware choices.
A Fixed-Point Introduction by Example
Christopher Felton walks through binary fixed-point representation with clear examples and a simple W=(wl,iwl,fwl) notation. He argues for designing to range and resolution rather than bit counts, then shows how multiplication and addition affect bit growth and alignment. These concrete examples make it easy to see why rounding, resizing, and radix-point bookkeeping are essential in DSP implementations.
Python scipy.signal IIR Filtering: An Example
Christopher Felton walks through using scipy.signal IIR filters to demodulate PWM signals, using spectrum and spectrogram analysis to show what works and what does not. He demonstrates using filtfilt to avoid phase delay, compares a single narrow IIR to a very high order FIR, and shows how staged IIR filtering and multirate ideas give much better attenuation. Includes an FPGA-ready MyHDL PWM model.
Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
Simple Concepts Explained: Fixed-Point
Fixed-point is the bridge between real-world values and integer arithmetic, and this post makes that bridge tangible with a hands-on ADC-to-gain example. It walks through mapping voltages to Q-format integers, choosing gain resolution in bits, and how multiplication adds bit growth and produces quantization error. Read it to build intuition for practical fixed-point choices when implementing DSP on FPGA or ASIC.
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
Spline interpolation
Markus Nentwig provides a cookbook for segmented cubic spline interpolation that turns scattered or noisy data into efficient fixed-point functions. The article shows how to build third-order polynomial segments with explicit value and slope control via basis functions, solve scaling factors by least-squares in Octave/Matlab, and export coefficients for Verilog RTL evaluation using the Horner scheme and practical fixed-point tips.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
DSP Algorithm Implementation: A Comprehensive Approach
This post lays out a practical pathway for taking DSP algorithms from high level simulation to production hardware, comparing GPP, DSP, FPGA and ASIC platforms. It presents a stepwise methodology starting with nested loop programs, then exposing parallelism with data flow graphs, using SystemC transaction level modeling to bridge to Verilog or VHDL, and explains why that flow speeds design and simulation.
Signed serial-/parallel multiplication
Struggling with costly wide adders for signed multiplication on FPGAs? Markus Nentwig unpacks a neat bit-level trick that turns two's-complement signed-signed multiplication into a serial-parallel routine using only a one-bit wider adder. Learn how flipping sign bits and a small, controlled constant cancel lets you avoid full sign-extension, and get a parametrized Verilog RTL plus synthesis notes to try it yourself.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
A Fixed-Point Introduction by Example
Christopher Felton walks through binary fixed-point representation with clear examples and a simple W=(wl,iwl,fwl) notation. He argues for designing to range and resolution rather than bit counts, then shows how multiplication and addition affect bit growth and alignment. These concrete examples make it easy to see why rounding, resizing, and radix-point bookkeeping are essential in DSP implementations.
Python scipy.signal IIR Filtering: An Example
Christopher Felton walks through using scipy.signal IIR filters to demodulate PWM signals, using spectrum and spectrogram analysis to show what works and what does not. He demonstrates using filtfilt to avoid phase delay, compares a single narrow IIR to a very high order FIR, and shows how staged IIR filtering and multirate ideas give much better attenuation. Includes an FPGA-ready MyHDL PWM model.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Signed serial-/parallel multiplication
Struggling with costly wide adders for signed multiplication on FPGAs? Markus Nentwig unpacks a neat bit-level trick that turns two's-complement signed-signed multiplication into a serial-parallel routine using only a one-bit wider adder. Learn how flipping sign bits and a small, controlled constant cancel lets you avoid full sign-extension, and get a parametrized Verilog RTL plus synthesis notes to try it yourself.
Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
Spline interpolation
Markus Nentwig provides a cookbook for segmented cubic spline interpolation that turns scattered or noisy data into efficient fixed-point functions. The article shows how to build third-order polynomial segments with explicit value and slope control via basis functions, solve scaling factors by least-squares in Octave/Matlab, and export coefficients for Verilog RTL evaluation using the Horner scheme and practical fixed-point tips.
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
Instantaneous Frequency Measurement
Measuring carrier frequency quickly and with minimal data matters in radar and signal characterization. Parth Vakil explains the delay-and-multiply instantaneous frequency measurement technique, shows how analytic signals and multiple delays resolve the 2π ambiguity, and demonstrates noise, phase-wrapping, and interferer effects using MATLAB code. He also outlines practical mitigations like phase unwrapping and channelization.
Simple Concepts Explained: Fixed-Point
Fixed-point is the bridge between real-world values and integer arithmetic, and this post makes that bridge tangible with a hands-on ADC-to-gain example. It walks through mapping voltages to Q-format integers, choosing gain resolution in bits, and how multiplication adds bit growth and produces quantization error. Read it to build intuition for practical fixed-point choices when implementing DSP on FPGA or ASIC.
