5G NR QC-LDPC Encoding Algorithm
Lyons Zhang breaks down the 5G NR QC-LDPC encoding structure, emphasizing the circulant permutation matrices and why QC-LDPC suits simple hardware. The post defines the Q(P) and Q(-1) notation, summarizes BG1 and BG2 dimensions and selection rules, and shows how the parity-check matrix is partitioned for practical encoder implementations.
Polar Coding Notes: A Simple Proof
Lyons Zhang presents a compact, elementary derivation of channel polarization for binary-input discrete memoryless channels. The note leverages Mrs. Gerber's Lemma to bound conditional entropies and follows the Alsan-Telatar averaging argument to show mediocre channels vanish. The proof sidesteps martingale convergence and recovers the standard result that the fraction of good channels approaches the channel capacity.
Polar Coding Notes: Channel Combining and Channel Splitting
Lyons Zhang walks through the core algebra of polar coding, showing how channel combining builds the vector channel W_N from N copies of a binary-input DMC using the polar transform G_N = B_N F^{⊗n}. The notes then define channel splitting, derive the coordinate-channel transition probabilities from the chain rule, and present the recursive formulas that let you compute W_{2N}^{(2i-1)} and W_{2N}^{(2i)} from W_N^{(i)}.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
5G NR QC-LDPC Encoding Algorithm
Lyons Zhang breaks down the 5G NR QC-LDPC encoding structure, emphasizing the circulant permutation matrices and why QC-LDPC suits simple hardware. The post defines the Q(P) and Q(-1) notation, summarizes BG1 and BG2 dimensions and selection rules, and shows how the parity-check matrix is partitioned for practical encoder implementations.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
Polar Coding Notes: Channel Combining and Channel Splitting
Lyons Zhang walks through the core algebra of polar coding, showing how channel combining builds the vector channel W_N from N copies of a binary-input DMC using the polar transform G_N = B_N F^{⊗n}. The notes then define channel splitting, derive the coordinate-channel transition probabilities from the chain rule, and present the recursive formulas that let you compute W_{2N}^{(2i-1)} and W_{2N}^{(2i)} from W_N^{(i)}.
Polar Coding Notes: A Simple Proof
Lyons Zhang presents a compact, elementary derivation of channel polarization for binary-input discrete memoryless channels. The note leverages Mrs. Gerber's Lemma to bound conditional entropies and follows the Alsan-Telatar averaging argument to show mediocre channels vanish. The proof sidesteps martingale convergence and recovers the standard result that the fraction of good channels approaches the channel capacity.
5G NR QC-LDPC Encoding Algorithm
Lyons Zhang breaks down the 5G NR QC-LDPC encoding structure, emphasizing the circulant permutation matrices and why QC-LDPC suits simple hardware. The post defines the Q(P) and Q(-1) notation, summarizes BG1 and BG2 dimensions and selection rules, and shows how the parity-check matrix is partitioned for practical encoder implementations.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
Polar Coding Notes: Channel Combining and Channel Splitting
Lyons Zhang walks through the core algebra of polar coding, showing how channel combining builds the vector channel W_N from N copies of a binary-input DMC using the polar transform G_N = B_N F^{⊗n}. The notes then define channel splitting, derive the coordinate-channel transition probabilities from the chain rule, and present the recursive formulas that let you compute W_{2N}^{(2i-1)} and W_{2N}^{(2i)} from W_N^{(i)}.
Polar Coding Notes: A Simple Proof
Lyons Zhang presents a compact, elementary derivation of channel polarization for binary-input discrete memoryless channels. The note leverages Mrs. Gerber's Lemma to bound conditional entropies and follows the Alsan-Telatar averaging argument to show mediocre channels vanish. The proof sidesteps martingale convergence and recovers the standard result that the fraction of good channels approaches the channel capacity.
