CIC bus width

Started by duemilaventivalvole 3 weeks ago3 replieslatest reply 5 days ago138 views

Hi guys, I took a look to

"A beginner's guide to Cascaded Integrator-Comb (CIC) filters"

and I am confused about registers width:

register bit widths = 12+3log2(8)=12+33=21bits               (11)

In the formula above I start from 12 bit bus, filtering values using a 3th order sinc filter, with decimation factor 8.

I am trying to create a 24 bit ADC with custom filters so I need FPGA to filter sigma-delta modulator output.

First filter is a fixed decimation factor (by 8) 5th order sinc filter.

1 + [5*log(8)] = 16 bit

Then I have following filters:
Sinc2 = 4th order, decimation factor by 2
Sinc3 = 5th order, decimation factor by 2
Sinc4 = 6th order, decimation factor by 2

I need programmable paths:

- Sinc1 => Sinc2 => Sinc3 => Sinc4
- Sinc1 => Sinc3 => Sinc4
- Sinc1 => Sinc4

So, Sinc2 should work with 16+(4*1)=20 bit registers
Sinc3 = 20+(5*1)=25 bit registers
Sinc4 = 25+(6*1)=31 bit registers

I could use 31 bit registers for all filters, then get only 24 bits for output values, am I right?

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Reply by DanBoschenMarch 25, 2024

The accumulator(s) in the CIC filter are allowed to overflow once in the time duration of the subtractions in the comb(s), as long as the accumulators properly wrap on overflow. This is because with two’s complement subtraction, the difference is maintained in an overflow condition as long as the true difference is less than the total max to min value set by the bit width. This sets the precision needed for the accumulator in a first order CIC and accumulators for higher order CICs starting with the input and output precision targets.  

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Reply by gretzteamMarch 25, 2024

Design the hardware to be able to handle your worst case bit growth.

Left shift your input by the difference in wordlength requirements for the other cases. 

This allows for picking the answer always from the top bits. Also bottom bits won't toggle in the cases you need to left shift saving power. 

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Reply by engineer68April 8, 2024

More bits might be left away in case assumptions can be made regarding the utilization of the vector width - depending on the problem. Since this is related to FPGA - one can see the operation in detail in the simulation with e.g. ModelSim in case too many or not enough bits are taken. Unused and overdesigned bits will be removed by the synthesis (in most cases).