## Optimal Cascaded FIR Decimator design

Started by 3 years ago5 replieslatest reply 3 years ago373 views

I would like to design an FIR filter to decimate a high rate 1 bit signal to a low rate high bit signal. Due to implementation constraints I have fixed filter length constraints.

My setup is as follows: I decimate by 32 followed by a second stage of 6. My constraints are: every 32 one bit input samples I can apply a 256 tap 16 bit FIR (for the first stage), and every 8 first stage outputs I apply a 128 tap 16 bit FIR.

I believe this gives me an effective filter length of 32 * 128 + (256-32) = 4,320 input samples (or something close to this).

If I design a single stage FIR with some spec using 4,320 taps I get a filter(using remez or firls, etc), F. I think that, due to the constraints applied by the above, I cannot (necessarily) implement F as a two staged cascade as F might not be able to be expressed as a linear combination of the first stage.

How then do I design the two stages to be jointly as close to the filter spec as possible? In the past I've manually designed two filters and they've been good enough. Thanks

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Hello andrew,

I have looked at this problem a number of times and have reminded paeople tht when you are filting the output of a 1-bit sigm-delta, with a fir filter, ther are no multiplies because the input samples are 1-bit wide. there are only adds! If you fold the resampler into the FIR filter you have a polyphase filter with no multiplies that down samples as well as reduces BW. I presented a paper at a conference that was dedicated to CIC filters and my message was, don't use a CIC for 1-bit data, use the polyphase filter... A whole bunch of paper were written later presenting the same argument. I did the same thing for the sigma delta ADCs in cell phones and reduced power consumption while improving spectral envelopes! see attached paper

ISCAS_CIC_3.pdf

fred h

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Thanks a lot, I'll go through your paper. In reality I won't be performing any multiplies in the first stage but I tried to simplify my question as it was getting long.

I have also done this before and, likewise, concluded that a polyphase FIR was the way for the architecture I was targetting.

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If your focus is multipliers then a single filter with polyphase structure for 1 bit input might be better than the multiplier-less CIC. But memory requirements for full filter polyphases are still needed and the adders may be wide or very wide. So it depends on available resources and platforms.

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