David Cooke (@ees3dc)
OK, so my link needs to have a RRC filter. You only specify roll off factor rather than cut-off etc. Can I make the interpolating filter a RRC or do I need RRC first...
Yes. In actual fact I think I need x32 to run the DAC at 4700 Msps and I have demonstrated the hardware interface runs at this speed. You use the FPGA's OSERDES...
OK, so attached are 2 sets of waveforms. The top set is my amended implementation that got rid of those artefacts and I think is what is meant by Fs/4, but as discussed,...
Sorry, could you explain how I upsample please? Is that "zero-stuffing" where I take the modulated signal, lets call that sample sequence S0, S1, S2, S3... and...
Thank you for the reply. Yes, I'm using +1 and -1 for the multiplier as this results in a simple XOR. I have changed the FPGA to option A as I discussed with KAZ...
Thanks for the help. I only found out about this scheme by a few sentences in a paper on the web. Is there some online text that discusses this method please? Is...
Not sure if it helps. But this is how I would implement option A.A mod.JPGThe DAC multiplexes the 4 inputs 1 at a time.
I hope I'm not frustrating you.. I don't know what you mean by up4. I have updated the diagram to show when these "samples" go to the DAC.A or B.JPGIs there some...
You and someone else on this forum have said that this technique is well known but I have not found anything on the web. I may be that I don't know what to search...
Hmmm, I think you are saying I need to implement B in the attachment? If so then that presents a problem because I have root raised cosine filtering and each data...
When you say lobes, is that harmonics because of the crude sin wave? Or is a lobe something different? I'm not sure how you can avoid this issue when you create...
I don't understand your message that "the mixer must use one same of each to produce one product." I beleive that the mixer is running at the sampling rate, First...
PLease see this attahcment. Digital Modulator.JPGThis works in that it does demodulate - just I have those artefacts.
Correct. I "multiply" (xor) I with "1100"I "multiply" (xor) Q with "1001"then I add them together. That makes: 2, 1, 0, 1. And if you take the DC offset away,...
Its an e2V RF DAC (they don't have many in the range - same device just different max sample rates) but to be honest, I see the same issue with a completely different...
Digital Modulator.JPGApologies, you are correct. That is how I am mixing it up. and yes, the idea is to take an nth image which looks like it could work, just not...
The DAC has several modes: NRZ, RTZ, RF etc. The DAC is in RF mode. The datasheet states that a weakness of RF mode is Fs clock spurs. Indeed, they disappear when...
DAC Baseband Response No Modulation.JPGDAC Baseband Response.JPGThe signal was created as a carrier of Fs/4, ie: +1, 0, -1, +1.....There is no mixing, this is all...
Attached is an RF-DAC output of a modulated IQ signal.Signal is generated with an FPGA with a simple "F/4" I-Q modulator. The RF-DAC sample frequency is 4700 MHz....
I believe the only viable DAC is the e2V EV12DS460A 7GSa/s DAC. The next fastest DAC is the AD719x series but they don't appear fast enough. I am flexible on the...
Direct RF.JPGThanks, I will try to dig out a copy... I attach some numbers of what I'm trying to achieveI am wanting to output from a DAC a modulated carrier at
8.2...
Thank you both for the reply. Apologies, but I should have pointed out that my I,Q outputs are already 12 bit wide root-raised cosine filtered and producing 4...
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