Shai Kon (@Shaiko)
weetabixharryYes, they are derived from the same XO on the board.My FPGA system clock is in the range of 300 MHz.So :1.The incoming samples should cross from the...
Hi, I understand the concept but trying to achieve a better understanding how it would look in hardware. My goal is to implement the filter in hardware.
So the architecture you have in mind clocks the ADC samples into h1,h2,h3,h4 using the ADC clock while the filters themselves together with the logic that calculated...
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