In the analog days, without the luxury of an FFT to create a spectrogram from say 1-Hz-wide bands from 20 Hz to 1000 Hz, we would use banks of analog filters to reconstruct 1/3 octave bands from 20 Hz to 1000 Hz from the data divided up into 1-Hz-wide bands. Each one of the filters would exclude frequencies outside the octave for that filter.

Today, is the approximate practical upper limit of creating a spectrogram digitally? Does modern DSP hardware and software make it possible to create a spectrogram for data from 20 Hz to 100 kHz or from 20 Hz to 200 kHz? The data would have to be sampled at a very high a frequency. Nyquist’s Rule says that the data with the highest frequency of 200 kHz would have to be sampled at 400 kHz but other things need to be taken into account.  For example, digital filters are not perfectly band limited; so the sharpness of the filter needs to be taken into account.

I've heard that for digital optical signals (pulses) of light transmitting information through a fiber-optic cable, the physical limit is the range of electromagnetic signals the fiber-optic cable will carry; i.e., as the pulses are made shorter and the bandwidth will begin to extend beyond the visible spectrum.  The bandwidth of the visible spectrum is approximately 430–770 THz. Creating a spectrogram of data over that range would require a high sampling rate.

Perhaps someone could provide an approximate practical maximum digital data sampling rate or provide an example of commercial hardware or software that would be able to produce a spectrogram of data over a wide frequency range say beginning at 20 Hertz and what that maximum spectrogram frequency could be approximately? 

Thank you.

John

It's really a function of getting the data acquired.  There's no solid answer because speed, resolution, and cost are one of those classic trade-off triangles.  But you can get monolithic ADC chips with 100MHz sampling rates these days, and there are FPGAs that will keep up with them.

Thank you.  The information really helps.

In modern FPGAs we can run digital systems @ clock rates of 400~500MHz. ASICs can do more.

But from DSP perspective (For Fs) you need to take into account upsampling rate of signal acquired from ADC or pushed into DAC.

I very much appreciate the information.  It really helps.

Don't forget that cost is a nonlinear function of sampling frequency as well. I don't know what the exponent is, but it's definitely >1.

I would add that on hardware targets (FPGAs/ASICs) you are not limited to the clock rate of the device. You can create Super Sampling Rate architectures on which you can handle sampling rates much faster that the system rate.

Last June I created a design for a customer for an ADC at 1250MHz on a 250MHz FPGA system clock. As soon as your ADC can provide multiple lanes at a lower rate you can do whatever you want.