Digital PLL's -- Part 1
We will use Matlab to model the DPLL in the time and frequency domains (Simulink is also a good tool for modeling a DPLL in the time domain). Part 1 discusses the time domain model; the frequency domain model will be covered in Part 2. The frequency domain model will allow us to calculate the loop filter parameters to give the desired bandwidth and damping, but it is a linear model and cannot predict acquisition behavior. The time domain model can be made almost identical to the gate-level system, and as such, is able to model acquisition.
Summary
This paper demonstrates time-domain modeling of digital phase-locked loops (DPLLs) using MATLAB (and Simulink), showing how a DPLL can be represented nearly identically to a gate-level implementation. Part 1 focuses on non-linear time-domain behavior and acquisition modeling; a companion Part 2 covers linear frequency-domain loop analysis for bandwidth and damping design.
Key Takeaways
- Build a time-domain MATLAB/Simulink model of a digital PLL that mirrors gate-level behavior.
- Simulate and analyze acquisition and lock transients that frequency-domain (linear) models cannot predict.
- Configure and connect core DPLL blocks (phase detector, loop filter, NCO/VCO) for realistic timing and nonlinearity.
- Validate time-domain models against intended hardware behavior to diagnose acquisition failures and transient effects.
Who Should Read This
DSP, communications, or control engineers (intermediate to advanced) who design or simulate digital PLLs and need practical MATLAB/Simulink guidance for modeling acquisition and gate-level behavior.
Still RelevantAdvanced
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