This blog describes several DC removal networks that might be of interest to the dsprelated.com readers.

Back in August 2007 there was a thread on the comp.dsp newsgroup concerning the process of removing the DC (zero Hz) component from a time-domain sequence [1]. Discussed in that thread was the notion of removing a signal's DC bias by subtracting the signal's moving average from that signal, as shown in Figure 1(a).

Figure 1.

At first I thought such a DC removal scheme would have the very poor passband peak-peak ripple performance of roughly 13 dB because of the 13 dB stopband ripple of a moving averager. But upon modeling this DC removal scheme I found that its passband behavior was better than I had expected. My modeling involved a computationally efficient D-point moving averager (MA), shown in Figure 1(b). The bottom path, in Figure 1(b), is a simple delay line having a length equal to the averager's group delay, (D-1)/2 samples. This enables us to time-synchronize the averager's v[n] output with the x[n] input in preparation for the subtraction operation.

The D-point moving averager (MA) in Figure 1(b) has a transfer function defined by

The second ratio in Eq. (1) is merely a recursive running sum comprising a D-length comb filter followed by a digital integrator. There are two delay lines in Figure 1(b); the bottom path's (D-1)/2 length delay, and the comb subfilter's delay line of length D within the MA.

This DC removal network's passband performance, when D = 31, is shown in Figure 1(c). (The frequency axis value of 0.5 corresponds to a cyclic frequency of half the input signal's F_s sample rate.) While the network has the desired infinite attenuation at zero Hz, its passband peak-peak ripple is unpleasantly large at 2.9 dB. We can do better, as we shall see.

If D is an integer power of two the 1/D scaling in (1) can be performed using a binary right shift by log₂(D) bits, making Figure 1(b) a multiplier-free network. However, in that scenario the MA's group delay is not an integer number of samples, making it difficult to synchronize the delayed x[n] and the v[n] sequences. To solve this problem we can use two cascaded D-point MAs as shown in Figure 2(a). Because the cascaded MAs have an integer group delay of D-1 samples, we can be clever and tap off the first moving averager's comb delay line eliminating the bottom-path delay line in Figure 1(b). This way we still only need implement two delay lines in Figure 2(a), one delay line for the comb subfilter in each MA.

Figure 2.

The magnitude response of the Figure 2(a) dual-MA DC removal network, for D = 32, is shown in Figure 2(c). In that figure we show the DC removal filter's passband with its narrower transition region width and a much improved peak-peak ripple of 0.42 dB. What we've created then is a linear-phase, multiplierless, DC removal network having a narrow transition region near zero Hz.

Happily, it's worth noting that standard tapped delay-line, linear phase, highpass FIR filter designs using least-squares error minimization, or the Parks-McClellan method, require more than one hundred taps to approximate our D = 32 DC removal filter's performance.

On a practical note, the MAs in Figure 2(a) contain integrators that can experience data overflow. (An integrator's gain is infinite at DC.) Using two's complement fixed-point arithmetic avoids integrator overflow errors if we ensure that the integrator (accumulator) bit width is at least:

where q[n] is the input sequence to an accumulator, and ékù means: if k is not an integer, round it up to the next larger integer.

For an even narrower transition region width, in the vicinity of zero Hz, than that shown in Figure 2(c), we can set D to a larger integer power of two, however this will not reduce the DC removal network's passband ripple.

At the expense of three additional delay lines, and four new addition operations per output sample, we can implement the linear phase DC removal filter shown in Figure 3(a). That quad-MA implementation, having a group delay of 2D-2 samples, yields an improved passband peak-peak ripple of only 0.02 dB, as shown in Figure 3(b), as well as a reduced-width transition region relative to the dual-MA implementation.

Figure 3.

The DC removal network in Figure 3(a) contains four 1/D scaling operations which, of course, can be combined and implemented as a single binary right shift by 4log2(D) bits. So the bottom line to this blog is that at the expense of multiple delay lines, it is possible to efficiently perform linear-phase DC removal.

[1] Posts during July 31 - August 8, 2007, Subject: "Regarding DC removal filter".

an2or wrote:

lishenghu365 wrote:

bluewhale wrote: