(@srid)
Yeah, I understand it's never ending process for improvement and has to stop at some time, considering cost,time,etc. I thought it would be a good learning for...
How to select the optimal filter line up for the Digital Down Converter implementation in FPGA? The input data rate is 100 MSPS and the required decimation factor...
makes sense Kaz. Which is the better approach to keep the gain ~1. Scale up the coefficients or rounding 15 bits and taking care of overflow ?
With the Impulse scaled to max value (+32767), I get the output = coeffs value / 2. That's the reason I posted the question in first place to understand why. For...
Testing in simulation. I might be doing something wrong, will look at them more closely. Thank you for the help !
Yes Kaz. I use both FIR and CIC filters.for FIR filter, the coeff sums before scaling is ~1. The max coeff is 32767, the sum of signed coeffs are 65535 and the absolute...
As Kaz pointed out, the FPGA got plenty of registers. CIC filter is implemented with full precision at the each stage and the rounding is done at the final stage....
How does the rounding work with the CIC filters? I use 5 stage CIC filter to interpolate the input by 36.
Thanks Kaz. It is low pass filter. You mean increasing the gain by multiplying the "output" by interpolation factor ?
The DC gain is ~1 (0.9999. Sum of all the co-efficients). The maximum gain is 65535 (sum of absolute 16 bit co-efficent values).
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