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The 10 bit resolution is the minimum that i can accept. The only missing information is the settling time on the datasheet, i don't understand if i cannot see it...
Thank you for the reply. I agree with you about the attenuation, and thanks for the suggestion. I'm not really interested in how much bandwidth to capture i just...
Hi, i'm new to signal processing. I probably have not understood
properly the following topic: i'm trying to use the XADC analog to
digital converter on my FPGA....
Sorry i mean that 10 Khz is obtainable only if you use a multirate stage cause using a single stage results in extreme lenght of the filter. 500 Mhz is a problem...
ok, everything should be clear now. In the first case the transition band start at around 50 Mhz as expected because i chose a decimation factor of 5. Clearly in...
ok thank you, i was not clear at all. I Perfectly agree and understand what you say about filtering before decimation, in the same way that is used to do with an...
Hi, i'm new to DSP so i'd like to understand something about decimation.
This is what i have : a sinusoidal signal,about 200MHz sampled with a
500 MSPS ADC then...
Hi jhondyson10 and thanks for your answer.Sorry but i have not undertood the most part of your message because i have to study better the IIR filters but i surely...
Hi Neil,thanks a lot for sending this pdf, i am reading it. It seems that this filter design is a spreaded problem. I will do some research on IIR filter to understand...
hi audiomath and thanks for your reply.I mentioned phase sensitive detection to deal with the tecnic used in the lock in to carry out the frequency component buried...
Hi, thank you for your answer. I’ll try to explain what I want to simulate with this design. The full design involves also a DAC and an ADC that I am not using...
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