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(@ahmadzaklouta)


Re: How to parallelize polyphase FIR resampling filters

Reply posted 7 months ago (06/16/2025)
I am doing a QPSK transmitter. The symbol rate is 2.5GHz which is way higher than the FPGA clock (500MHz). becaue the DAC run at 5GHz, the interface accept 10 samples...

Re: How to parallelize polyphase FIR resampling filters

Reply posted 7 months ago (06/16/2025)
Hey!I am trying to do similar thing but just with interpolation. The DAC we are using is running at 5GHZ and accept 10 samples per clock cycle. our clock is 500MHz...

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