## Digital lock in amplifier on FPGA

Started by 6 years ago●8 replies●latest reply 6 years ago●946 viewsHi there, i'm just a young player with FPGA, digital design and also signal processing. I'm trying to implement a digital lock in amplifier. The main problem of this design are the 2 low pass filters that are supposed to let pass only (ideally) the dc component of the signal according to the functional principles of lock in detection. In my simulink simulation i chose to use FIR filters for the purpose but the minimum number of multiplier that i achieved was around 700 that is too much. I Tried to reduce the sampling frequency with a decimation to relax the filter and achieved 300 multipliers that is also a lot. I don't know IIR filters but i read somewhere that the important feature of this kind of filter is the low order required. Can anyone please help me to understand if this kind of filter is suitable for my design? thanks a lot.

What kind of performance are you expecting? (for example in dB/octave)

Sometimes a PLL loop filter can be very simple, sometimes not. It depends on your requirements. How far away is the output frequency from the clock frequency? What is the sampling rate? How important is it to have low phase ripple in the output?

Hi, thank you for your answer.

I’ll try to explain what I want to simulate with this design. The full design involves also a DAC and an ADC that I am not using in this simulation, in fact I only want to estimate the weight of the 2 filters of the lock ins in terms of multipliers.

I want to generate with a DDS generator (in the FPGA) 2 sinusoidal signals (for example 40 Mhz and 100 Mhz) that are used also as reference signals for the lock in. I need to convert these signals with a DAC so that they can perform some analog functions which I am not involved. For this part I need a clock frequency that allows me to generate these signals and I think it must be at least 200 Mhz. After the 2 signals are converted with a DAC with a sampling frequency that I have to choose. The signals that comes back are completely buried in the noise, so I have to use an ADC and a low pass filter (to prevent aliasing) to let the FPGA work with them to perform the phase sensitive detection. Once I choose the sampling frequency for the ADC the next block is the lock in amplifier (for example the one for 40Mhz). The 2 filters are critical for the entire design because the number of multiplier required seems to be very high. I tried to do a decimation to reduce the sampling frequency for the filters some value around 10 Mhz but the order is also too high for my requirement, so I was thinking if the IIR filter may be a solution for this problem. I think that phase ripple is important, but I cannot say how much is involved. With some random tries I find that the IIR filter works well for the amplitude detection and not very well for the phase detection (perhaps high phase ripple?). This is what I have in mind, but I am a bit confused so be patience with me if you can. Thanks again.

Sorry, I think I misunderstood your question.

If I'm reading this right, you want to (A) generate two signals using DDS, and (B) you're trying to characterize the required LPF's for very noisy return signals at those frequencies.

First, yes, if one DDS will be working at 100 mHz, your clock will need to be at least 200 mHz if you generate the signal directly.

Second, are the return signals phase modulated? You mention "phase sensitive detection". If the signals do not vary significantly in phase or frequency, the non-linear phase characteristic of the IIR filter shouldn't be a problem. There is also a way to eliminate non-linear phase response from the discussion if you can afford to run two IIR filters with a forward-reverse connection. Dr. Steven Smith explains this in chapter 19 of his book "The Scientist's and Engineer's Guide to Digital Signal Processing": http://www.dspguide.com .

Another possible method is FFT, or "Fast" convolution, using either overlap-add or overlap-save. I'm not an FPGA expert, but I believe Simulink does have the ability to synthesize an FFT. If the signals are decimated and FFT convolution is used, you can greatly reduce the number of required operations as compared to a FIR filter.

I hope you find some of this useful.

I mentioned phase sensitive detection to deal with the tecnic used in the lock in to carry out the frequency component buried in the noise. In my case is a simple 100 MHZ sinusoidal signal. This signal passing to DAC ADC and some filter is phase modulated so i have to take account in some post correction. I cannot say how much the signal vary in phase but with the lock in i have to be able to carry out the initial amplitude and phase of the signal.

Thank you for linking this book, i'm currently studying the chapters dedicated to filters so i hope i will understand the problem better. I've found it very useful thank tou very much.

Gabrics,

I notice there are a lot of articles on this subject on the web. For example:

Microchip App note AN1115: Implementing Digital Lock-In Amplifiers Using the dsPIC DSC

I suggest you read up on various implementations to give yourself a running start. Regarding IIR filters, it is true that they can be useful when bandwidth is much less than sample rate. But there are limits to how low you can go, and performance depends on how they are implemented. Note also they are not linear phase.

regards,

Neil

thanks a lot for sending this pdf, i am reading it. It seems that this filter design is a spreaded problem. I will do some research on IIR filter to understand if the non linear phase may be a problem in my case. In my simulation i see that the IIR filter works well for the amplitude detection and not very well for the phase. I found surprisingly that works well also with a very low SNR so i must to understand better how to optimize it.

thank you very much,best regards.

Myself, I am not competent in the area of digital PLLs, but I can help with IIR filter design. I have a simple subroutine that converts from a '2nd order' / '2nd order' prototype analog filter to a digital filter using the bilinear transform. It handles the sample rate issue, and the warping. Of course it is only useful for the case where the bilinear transform is appropriate -- but makes it easy if you want a filter design (based on an analog filter) to be agile WRT the sample rate. I also have a relatively easy to use window style FIR filter subroutine which supports the online creation of fixed standard windowed filter behaviors and still be sample rate agile. (currently it only supports VonHann, but has the architecture to be upgraded to multiple window types.) This is a well known algorithm, but it seems to be difficult to find clean/clear and easy to read implementations... So, I wrote my own. My implementation might have a few off by one problems, but works super well in my audio application.

The routines are simple (lots of little details, but simple), and written in a primitive C++. They are not fully tested -- I am currently using them for a fixed purpose so haven't tested all of the paths (using it for my DolbyA decoder.) I am willing to offer the routines privately before I clean them up, and publicly after they have been made to be pretty and better tested.

One MAJOR caveat when using filters like this -- sometimes a person forgets about the precision of the underlying math, so filter (coefficients) can easily underflow the number system. This happens very often when filtering low frequencies relative to the sample rate. Also, the FIR filter must have a minimum length given certain kinds of filters, or they will not have adequate skirts or even work well at all.

I can only help with a few little/common implementation details -- but willing to do so.

Sorry but i have not undertood the most part of your message because i have to study better the IIR filters but i surely take account the underflow in this particular case,thank you for advise.