I'm curious about the bit-width requirements of the accumulators in an Nth-order CIC filter with decimation ratio R and differential delay 1.

Clearly there is an upper bound that N log2 R additional bits, on top of the input width, would be sufficient; Hogenauer's paper in 1981 references this. If you have a 1-bit input and a 3rd-order CIC filter with R=1024, 31 bits would be sufficient.

My question is whether it is strictly necessary; I went through the thought process of a CIC filter processing f0[k] = 1-bit input of all zeros , compared to processing f1[k] = 1-bit input of all ones, and the maximum relative difference of the output of the last accumulator, comparing inputs f0[k] and f1[k], regardless of the initial state of the accumulators, of one accumulator, after R samples, is R; the relative difference of the output of the 2nd accumulator is R*(R+1)/2 (Rth triangular number); the relative difference of the output of the 3rd accumulator is R*(R+1)*(R+2)/6 (Rth tetrahedral number). As long as this relative difference doesn't cause wraparound aliasing between the two worst cases, there should be enough bits to represent the filter state.

But log2(R*(R+1)*(R+2)/6) is more than two bits smaller than log2(R^3)...

Can anyone point to the mistake in my reasoning?

I'm not sure how difficult it would be for the accumulator in a CIC filter, but sometimes a useful approach can be to derive the worst-case input signal (i.e. the input sequence which maximizes the amplitude at the specific circuit node of interest) ... and work backwards from there.

For example, if you were instead interested in the maximum value at the final output of the CIC filter (without decimation), then it would be sum(abs(h)) times larger than the maximum input value (where h is the finite impulse response of the CIC filter).

That result can be found by noticing that the worst-case input sequence in this case would be -1 where h<0, and +1 where h>0. (Where I have assumed a symmetrical input range [-1, 1]). From there, it's easy to calculate the maximum output value, sum(abs(h)).

My understanding is that the dc gain formula is for the output. Since each comb output requires one extra bit then I can say that each accumulator will need (31 bits - 3 bits).

Can you explain some of the terms?  When I think of CIC, I only think about a moving average filter (or moving sum).  When I think of filter order, I think of the number of states, which is one less than the number of taps of a general FIR.

Now if L is the length of the moving sum, we are adding L adjacent samples together in the accumulator before we first start subtracting samples.  So the accumulator has to have log2(L) more bits on the left because we are adding L numbers.

Just for a common reference to look at, I am looking at https://wirelesspi.com/cascaded-integrator-comb-ci...