Hi All,

I've got an FPGA with number of 'DSP' blocks (basically a 16 bit multiplier that can add to its result) and was looking to use that with some SDR code to do filtering on my IQ stream. My architecture is basically similar to the ADALM-PLUTO in that it has a CPU component and a fabric component which are integrated via some clever DMA/memory-bus logic. And while there are many proprietary "we'll generate black box FPGA code for you from your MATLIB/Octave code" or similar "give us your parameters and we'll spit out some code" there aren't many (any?) good examples of "This is a verilog module that implements a SQRT filter" kinds of things. Wondering if someone had come across a text book or appnote that had this sort of information I could learn from.

--Chuck

Hey Chuck,

Which FPGA are you using?  The family matters.

FWIW, I don't use any tools to do my RTL coding.  I use very basic routines to search for good coefficients and then implement taking the best advantage of the DSP blocks that are available to me in the Xilinx series 7 parts.

This is a paper I've made good use of:

https://arxiv.org/pdf/1610.03360

I 1st looked at it just for ideas on implementing a systolic FIR filter.  The more experience I had the better I was able to use what is in there.

There is also the two-path all-pass IIR filters that fit very nicely into the DSPs as well.  Just depends on what you need.

Cheers,

Mark Napier

Helpful paper, thanks! FPGA architecture is mostly Zynq (because Pluto/B210/ANTSDR etc), but I would love to build something with the Lattice chips (ICE40/ECP5) because they have good open source tool chains that are readily accessible.

Hi Chuck,

A good Xilinx DSP base documnet is their UG193 which still has some useful information on how the DSP blocks can be used. This gives you the base architecture and data cascading structures that a good filter implementation should follow. I think it misses off the pre-adder that's present in the DSP48E2 block as it wasn't around at this time but that's easy to include in symmetric filter implementations.

The Xilinx Vivado tool has a good verilog template for the DSP block, I would recommend using this (you can also find the code in their verilog coding guidelines documentation).

With these in mind, finding verilog code examples should be relatively easy. There was this entry a while ago at
https://www.dsprelated.com/thread/9337/dsp-rtl-lib...
ZipCPU has some tutorials and Github code which you should be able to find at https://github.com/ZipCPU/dspfilters

I couldn't find anything else that I would say was a good code example. I hope that these help.

Regards, Chris.

For my code I write Verilog wrappers that encapsulate a single DSP block that is configured for what I need in that instance and only what I need brought out to ports.  Makes the upper-level design much cleaner.

In the simulation source directory is DSP48E2.v.  I make an instantiation for this in my wrapper with all of the parameters listed and a comment for what each one does.  Same for all of the ports.  General rule of thumb for the data ports is that if you are not using one then leave it unconnected.  Especially true for the "edge connection" ports.

Except that I do tie off all the enables, connect all the resets.  Same for carry bits.

Also look at the DRC report in the implemented design.  Some of the warnings I ignore but some I've taken to heart.

Have fun,

Mark Napier

Hi Chuck,

You can try the following repo in GitHub. It is developed in Verilog and open source:

https://github.com/ahmedshahein/DSP-RTL-Lib

Regards,

Ahmed