Hello,

I have an application where I need to resample from one sample rate to another.  Pretty sure this will need a delay type or Farrow filter.  The ones I am familiar with usually work out to Fs/4.  Nice polyphase one ala fred harris I've used in the past could interpolate to Fs/4 with virtually no distortion.

Thing I'm looking at now I need to interpolate a wide band signal in a minimalist design.  Read very modest FPGA resources.

Specs:

In coming sample Rate Fs_in = 32 M samples/second.  Complex I/Q

Final sample Rate Fs_out = 120 * 2^17 = 15728640 Samples/second

Band of interest = +/- 4.13 MHz.  So total 8.26 MHz wide.

Out of band bleed in or distortion < 95 dB.

Desired In band ripple <= 0.05 dB.

Note I can rotate my band of interest down to DC at Fs_in before any other work.  Also I don't care about any other distortion/aliases outside my band of interest at Fs_out because they will be removed by very tight channel filters.

Problem is that there are a lot of unwanted strong signals around my band of interest at Fs_in.  Normally this would be a pre-filter followed by the interpolator and then maybe another clean up or say a half-band filter.  This would certainly work but I want to minimize resources.  An interpolator that works to Fs/2 would be nice but I don't know how to do that and again is likely expensive.

Doing a literature search now and will gladly take good suggestions.

Thanks in advance,

Mark Napier

Hi Mark,

So my understanding is you are looking for a polynomial interpolator with a lot of selectivity?  I'm probably missing something, but I don't think polynomial interpolation is likely to do that.

regards,

Neil

Hey Neil!

I'm looking for an overall design method.  Yes, a polynomial interpolator won't do it alone as it only works out to a fraction of the Nyquist zone.  Frequency components above that fraction will lead to artifacts in the output likely in the band of interest.  So yes typically it would require a band limiting filter 1st, then the interpolator and finally another filter to clean up after.

A polyphase/derivative interpolator (like the one on the Docsis upstream, ala fred harris) worked up to Fs/4 and as long as the input was band limited to less than Fs/4 no post filter was needed.  But it was an expensive beast.

I have seen an interpolator (in a slide presentation) that worked over the entire Nyquist zone but I wasn't in position to inquire about the design.

Currently dinking around looking for inspiration to descend.

Cheers,

Mark

Inspiration can be so fickle.  It usually seems to arrive when you're driving home from work -- which means don't work overtime.  Good luck!

Hello

Since your concern is implementation I am not sure what is next is helpful, but let's try.

There is clearly no functional difficulties here. As you said it is possible and probably useful to use a decimation prefiltering (typically 66 FIR coeff will dot it, or a cascade of 2 FIR 32) and work at 16 MHz with a clean interpolator with a moderate number of coeff (like 10 or 12)..

The optimal interpolator is the Wiener's filter but it converges to the truncated SHANNON's filter when there is no oversampling margin. In your case you have plenty of margin, so the interpolation error will be very small within your 8.26 MHz bandwidth. 

You can then virtually oversample your initial signal and then select dynamically the right sample by linear interpolation to get the right output sampling rate. 

No idea how you can do that in FPGA, but, without constraints, in principle you can do it.

Regards

Laurent

Hi Mark. I don't have an answer, but maybe an adjacent application to feed your lit search... about 15 years ago I was working on digital channelizer of the FM band.  Very similar requirements to yours.  I'm out of the loop now, but there must be a lot of publications on that topic by now.  It was pretty red hot 15 years ago.

You didn't say which FPGA resource(s) are limited, but if the main bottleneck is multipliers, then you should clock this component as fast as possible and share multipliers between several filter coefficients.

Assuming your multipliers need to process at the 15.73 Msps output rate, and you have a modern-ish FPGA, it should be very feasible to run your clock at >= 503.31648 MHz (which will reduce your number of multipliers by a factor of 32).

However, the resampling ratio of 1536/3125 looks pretty horrible for a polyphase resampler. You would need to store so many phases that you would probably lose a lot of block memories in that architecture.

Therefore, (depending on your performance requirements) I would seriously consider some kind of dumb filter-downsample architecture. The FIR filter would then have to run at 32 Msps (e.g. on a 512 MHz clock, with a factor of 16 resource saving). However, that FIR filter would be symmetric, so you could then use the (free) pre-adders in your FPGA's DSP slices to save a further factor of 2. So, you would still save a factor of 32, but this architecture is very simple to implement and has a very small memory requirement. (But bad filtering performance, if you don't implement all the filter phases).