## Issues regarding the implementation of integrator in GMSK modulator

Started by 3 weeks ago●4 replies●latest reply 2 weeks ago●104 viewsThis block works for me and seems to match what is in the communication block. It will do GMSK and GFSK.

First is the FIR to provide the shaping of a raw bit and interpolation. Next is a simple unipolar to bipolar conversion. Then the modulation gain with is the modulation index/(2 * samples_per_symbol). Next is the phase accumulator. Note this is scaled so that 1 = 2*pi. Also note the modulus function so that the phase is always in the range of [0,1). Next is the gain by 2*pi and the sin/cos lookup. The output from this block is baseband modulation so it must be interpolated and rotated up to your final IF frequency.

%Init code for the mask:

ph_init = ph_off/(2*pi); % Initial phase

Ts = Tb/sps; % Sample time (seconds)

t = linspace(-span/2,span/2,(sps*span+1));

alpha = sqrt(log(2)/2)/(bt);

h = exp(-(t*pi/alpha).^2);

h = h./sum(h); % FIR filter taps

Thank you so much for the great response, I really appreciate it. I also found the masking technique in simulink through your response only and found it very convenient.

I have implemented gmsk modulator with reference to your response and also tried with the implementation of gmsk demodulator. In demodulator, since the phase of the modulated signal needs to be extracted since the information is encoded in phase changes between symbols, I made use of a differential discriminator for that purpose using the multipliers and delay units. And then used a switch to provide a threshold level to get the output in binary. The below shown is the rough draft of the blocks. But however, I'm not getting a good value during error rate calculation. If possible, could you provide an insight on where I went wrong.

In the below shown figure, I and Q are the given inputs.

gmsk_demod.png

There isn't a figure in your response.

I will also say that demod of continuous phase modulation is a difficult problem. At least it is for me. I put together a few blocks tinkering with methods for burst demod. The receiver needs to get a close estimate of frequency, phase, and timing sync and start of packet in the preamble. These need to be close enough to be able to track with PLLs during the rest of the packet RX.

I could do some of these with various methods but the full solution would be to sample the whole packet and then post process. Not something I can do with a very modest FPGA.

I couldn't crack it and didn't find anyone who was able/willing help out so I gave up.

Also turns out that the class of IOT devices I am working with widely support GFSK so I used this as the lowest common denominator.

This type of receiver is much simpler. It finds the average frequency offset in the preamble by averaging. It also uses cross-correlation to find the center of the data eye. Then track the timing in the rest of the packet.

BTW, if you sign up for the DSP Online Conference there is a presentation from a couple of years ago that does a wonderful job covering timing synchronization in a receiver.

Hope some of this helps.

Mark Napier

Sure, this was helpful. Will check out the conference presentation.

Also, I've added the figure as an image, I hope it is visible now.