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I want to connect a fifo with width of 16 bit to C6415 EMIFA . To read the fifo using PDT ( peripherral device transfer ) The EMIFA has a 64 bit width SDRAM as the destanation for the transfer and the sorce is the fifo . ( like the Figure 10-63 in TI doc. SPRU190D ) . The qustion is if I preform a PDT write transfer from the fifo to the memory how will the data be writen in the memory ? will it be wirten in all the 64 bit byte after byte (first byte at byte 0 the next on byte 1 and then on byte 2 ...3 ..4 .. 5 and so on or it will be writen in byte 0,1 then on byte 8 , 9 ? |
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Fifo connection to C6415
Started by ●June 23, 2002
Reply by ●June 24, 20022002-06-24
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Hello > I want to connect a fifo with width of 16 bit to C6415 EMIFA . > The EMIFA has a 64 bit width SDRAM as the destanation for the In PDT mode, a single cycle to read the fifo and write to the SDRAM will be generated by the DMA & EMIF controllers. So you SHOULD use the same bus width for your SDRAM and your FIFO. If you simply wire your 16 bits fifo to EMIFA where the SDRAM is 64 bits, you will get into your fifo 1 WORD out of 4..... So you have 2 choices : - set your SDRAM on 16 bits (what a pity :) - use a 64 bits wide FIFO I suggest that you use a bus-sizing FIFO : see at IDT, they have fifo that that be 64 bits on one side and 16 bits on the other side. Note : I suppose that you know that PDT is not working on TMX silicon ? Regards, Jean-Michel MERCIER ------------------- dsp & imaging - www.ateme.com ATEME - 26 Burospace - 91573 BIEVRES Tel : +33 (0)1 69 35 89 73 (direct) Fax : +33 (0)1 60 19 13 95 |
Reply by ●June 24, 20022002-06-24
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Hi Gabi, Before you go to PDT remmeber this feature still not working, see errata from TI. Eli Keren -----Original Message----- From: drenger_gabi [mailto:] Sent: Sun, June 23, 2002 10:55 AM To: Subject: [c6x] Fifo connection to C6415 I want to connect a fifo with width of 16 bit to C6415 EMIFA . To read the fifo using PDT ( peripherral device transfer ) The EMIFA has a 64 bit width SDRAM as the destanation for the transfer and the sorce is the fifo . ( like the Figure 10-63 in TI doc. SPRU190D ) . The qustion is if I preform a PDT write transfer from the fifo to the memory how will the data be writen in the memory ? will it be wirten in all the 64 bit byte after byte (first byte at byte 0 the next on byte 1 and then on byte 2 ...3 ..4 .. 5 and so on or it will be writen in byte 0,1 then on byte 8 , 9 ? _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: Send an email to To Post: Send an email to To Leave: Send an email to Archives: http://www.yahoogroups.com/group/c6x Other Groups: http://www.dsprelated.com ">http://docs.yahoo.com/info/terms/ |
