GPIO and compiler switch -g

Hi,

I use GPIO to generate output signals with a minimum high pulse width of 
   240ns. I must use NOP for the timing, because I have no free timer. 
So I entered 72 NOPs (300MHz) delay and I got a pulse width of 180ns! It 
looks like there is a GPIO internal timing which is much slower than 
SYSCLK1. I had to adjust the number of NOPs (now 90), but I can live 
with it.

Then I turned compiler switch '-g' off and on. If full debug mode is
off 
the pulse width is 240ns with 90 NOPs. If full debug mode is on the 
pulse width is 380ns with 90 NOPs! I had a look at the listings. There 
is no difference in code between the set and clear GPIO. But where does 
the additional delay come from?

TIA

Gustl