Hello,
I have XCR3032XL CPLD in my design interface with TMS320C6412. CPLD is mainly
enabling/disabling latch signals (LEDIN, OEDO) based in chip enable (CE), write,
read signals from CPU. Below is the code:
It is using CE2, 0xa0000000 space. LEDIN, OEDO never get set to zero(lowest bit,
1110).
process(Addr, Wr, Rd, Reset, CE)
begin
if(Reset = '0') then
LED1 <= '0';
LED2<= '0';
endif
if( CE = '0') then
if( Wr='0') then
case Addr
when "00" LEDIN <= "1110";
when others LEDIN <= "1111";
end case;
if( Rd='0') then
case Addr
when "00" LEDO <= "1110";
when others LEDO <= "1111";
end case;
end if;
end process;
Please let me know what steps I need to take to make it work.
Thanks,
Yatin
_____________________________________
TMS6412 and CPLD
Started by ●February 18, 2009
Reply by ●February 18, 20092009-02-18
Yatin,
On Wed, Feb 18, 2009 at 6:32 AM, wrote:
> Hello,
>
> I have XCR3032XL CPLD in my design interface with TMS320C6412. CPLD is
> mainly enabling/disabling latch signals (LEDIN, OEDO) based in chip enable
> (CE), write, read signals from CPU. Below is the code:
Q1. Could you explain what you are trying to do??
Q2. Could you identify what signals that you are decoding in addition
to Wr, Rd, Reset, and CE??
mikedunn
>
> It is using CE2, 0xa0000000 space. LEDIN, OEDO never get set to zero(lowest
> bit, 1110).
> process(Addr, Wr, Rd, Reset, CE)
>
> begin
>
> if(Reset = '0') then
>
> LED1 <= '0';
>
> LED2<= '0';
>
> endif
>
> if( CE = '0') then
>
> if( Wr='0') then
>
> case Addr
>
> when "00" LEDIN <= "1110";
>
> when others LEDIN <= "1111";
>
> end case;
>
> if( Rd='0') then
>
> case Addr
>
> when "00" LEDO <= "1110";
>
> when others LEDO <= "1111";
>
> end case;
>
> end if;
>
> end process;
>
> Please let me know what steps I need to take to make it work.
>
> Thanks,
>
> Yatin
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
_____________________________________
On Wed, Feb 18, 2009 at 6:32 AM, wrote:
> Hello,
>
> I have XCR3032XL CPLD in my design interface with TMS320C6412. CPLD is
> mainly enabling/disabling latch signals (LEDIN, OEDO) based in chip enable
> (CE), write, read signals from CPU. Below is the code:
Q1. Could you explain what you are trying to do??
Q2. Could you identify what signals that you are decoding in addition
to Wr, Rd, Reset, and CE??
mikedunn
>
> It is using CE2, 0xa0000000 space. LEDIN, OEDO never get set to zero(lowest
> bit, 1110).
> process(Addr, Wr, Rd, Reset, CE)
>
> begin
>
> if(Reset = '0') then
>
> LED1 <= '0';
>
> LED2<= '0';
>
> endif
>
> if( CE = '0') then
>
> if( Wr='0') then
>
> case Addr
>
> when "00" LEDIN <= "1110";
>
> when others LEDIN <= "1111";
>
> end case;
>
> if( Rd='0') then
>
> case Addr
>
> when "00" LEDO <= "1110";
>
> when others LEDO <= "1111";
>
> end case;
>
> end if;
>
> end process;
>
> Please let me know what steps I need to take to make it work.
>
> Thanks,
>
> Yatin
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
_____________________________________
Reply by ●February 18, 20092009-02-18
Hi Mike,
Thanks for the quick response.
I have a external Latch and it has control signals LE. If LE goes low then data from the DSP is transparent to the outside world i:e; writing. For reading there is another signal OE, if that goes low then I am reading from the external world. As they are latch hence they need to be setup only one time duing startup.
Here is what I am trying to do:
1. set the external latch for writing, I am using CE2 address space, below is the snippet of the firmware for TMS320C6412:
main()
{
*(unsigned int*) 0xa0000000 = 0xff;
}
2. with step 1, I should have CE2 goes down and based on Wr/Rd, one of the VHDL case statement should gets executed.
3.
Hello,
>
>I have XCR3032XL CPLD in my design interface with TMS320C6412. CPLD is mainly enabling/disabling latch signals (LEDIN, OEDO) based in chip enable (CE), write, read signals from CPU. Below is the code:
>
>It is using CE2, 0xa0000000 space. LEDIN, OEDO never get set to zero(lowest bit, 1110).
>
>process(Addr, Wr, Rd, Reset, CE)
>
>begin
>
>if(Reset = '0') then
>
>LED1
_____________________________________
Thanks for the quick response.
I have a external Latch and it has control signals LE. If LE goes low then data from the DSP is transparent to the outside world i:e; writing. For reading there is another signal OE, if that goes low then I am reading from the external world. As they are latch hence they need to be setup only one time duing startup.
Here is what I am trying to do:
1. set the external latch for writing, I am using CE2 address space, below is the snippet of the firmware for TMS320C6412:
main()
{
*(unsigned int*) 0xa0000000 = 0xff;
}
2. with step 1, I should have CE2 goes down and based on Wr/Rd, one of the VHDL case statement should gets executed.
3.
Hello,
>
>I have XCR3032XL CPLD in my design interface with TMS320C6412. CPLD is mainly enabling/disabling latch signals (LEDIN, OEDO) based in chip enable (CE), write, read signals from CPU. Below is the code:
>
>It is using CE2, 0xa0000000 space. LEDIN, OEDO never get set to zero(lowest bit, 1110).
>
>process(Addr, Wr, Rd, Reset, CE)
>
>begin
>
>if(Reset = '0') then
>
>LED1
_____________________________________
Reply by ●February 19, 20092009-02-19
Hello Yatin,
It seems that VHDL code you have posted is having syntax errors.
Anyway I am re-writing the code considering your requirements; hope it will help.
process(Addr, Wr, Rd, Reset, CE)
begin
if(Reset = '0') then
LED1 <= '0';
LED2<= '0';
endif
if( CE = '0') and (Addr="00") then
if( Wr='0') then
LEDIN <= "1110";
else
LEDIN <= "1111";
end if;
if( Rd='0') then
LEDO <= "1110";
else
LEDO <= "1111";
end if;
end if;
end process;
-Ruturaj.
----- Original Message -----
From: y...@hotmail.com
To: c...
Sent: Wednesday, February 18, 2009 6:02 PM
Subject: [c6x] TMS6412 and CPLD
Hello,
I have XCR3032XL CPLD in my design interface with TMS320C6412. CPLD is mainly enabling/disabling latch signals (LEDIN, OEDO) based in chip enable (CE), write, read signals from CPU. Below is the code:
It is using CE2, 0xa0000000 space. LEDIN, OEDO never get set to zero(lowest bit, 1110).
process(Addr, Wr, Rd, Reset, CE)
begin
if(Reset = '0') then
LED1 <= '0';
LED2<= '0';
endif
if( CE = '0') then
if( Wr='0') then
case Addr
when "00" LEDIN <= "1110";
when others LEDIN <= "1111";
end case;
if( Rd='0') then
case Addr
when "00" LEDO <= "1110";
when others LEDO <= "1111";
end case;
end if;
end process;
Please let me know what steps I need to take to make it work.
Thanks,
Yatin
_____________________________________
It seems that VHDL code you have posted is having syntax errors.
Anyway I am re-writing the code considering your requirements; hope it will help.
process(Addr, Wr, Rd, Reset, CE)
begin
if(Reset = '0') then
LED1 <= '0';
LED2<= '0';
endif
if( CE = '0') and (Addr="00") then
if( Wr='0') then
LEDIN <= "1110";
else
LEDIN <= "1111";
end if;
if( Rd='0') then
LEDO <= "1110";
else
LEDO <= "1111";
end if;
end if;
end process;
-Ruturaj.
----- Original Message -----
From: y...@hotmail.com
To: c...
Sent: Wednesday, February 18, 2009 6:02 PM
Subject: [c6x] TMS6412 and CPLD
Hello,
I have XCR3032XL CPLD in my design interface with TMS320C6412. CPLD is mainly enabling/disabling latch signals (LEDIN, OEDO) based in chip enable (CE), write, read signals from CPU. Below is the code:
It is using CE2, 0xa0000000 space. LEDIN, OEDO never get set to zero(lowest bit, 1110).
process(Addr, Wr, Rd, Reset, CE)
begin
if(Reset = '0') then
LED1 <= '0';
LED2<= '0';
endif
if( CE = '0') then
if( Wr='0') then
case Addr
when "00" LEDIN <= "1110";
when others LEDIN <= "1111";
end case;
if( Rd='0') then
case Addr
when "00" LEDO <= "1110";
when others LEDO <= "1111";
end case;
end if;
end process;
Please let me know what steps I need to take to make it work.
Thanks,
Yatin
_____________________________________
Reply by ●February 19, 20092009-02-19
Ok, I found the mistake with my hardware. It is fixed now.
Thanks again for the quick reply.
-Y
Hello,
>
>I have XCR3032XL CPLD in my design interface with TMS320C6412. CPLD is mainly enabling/disabling latch signals (LEDIN, OEDO) based in chip enable (CE), write, read signals from CPU. Below is the code:
>
>It is using CE2, 0xa0000000 space. LEDIN, OEDO never get set to zero(lowest bit, 1110).
>
>process(Addr, Wr, Rd, Reset, CE)
>
>begin
>
>if(Reset = '0') then
>
>LED1
_____________________________________
Thanks again for the quick reply.
-Y
Hello,
>
>I have XCR3032XL CPLD in my design interface with TMS320C6412. CPLD is mainly enabling/disabling latch signals (LEDIN, OEDO) based in chip enable (CE), write, read signals from CPU. Below is the code:
>
>It is using CE2, 0xa0000000 space. LEDIN, OEDO never get set to zero(lowest bit, 1110).
>
>process(Addr, Wr, Rd, Reset, CE)
>
>begin
>
>if(Reset = '0') then
>
>LED1
_____________________________________
