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C6203'Xbus and syn FIFO

Started by hu guang ●October 17, 2002
Dear friend:
Hi, i know there are many experts on DSP in the discussion group.
Now i get a hard problem. I hope you can give me some advice and help.
We design a DSP and FPGA system,with a FIFO to connect both.
DSP: TMS320C6203
FPGA: XILINX Vertex XC2V3000
FIFO: IDT 72V36100, synchronous 64K*32
FPGA writes data to FIFO,and DSP reads data form FIFO by Expansion Bus(Xbus).
I has writen a HDL program ,so FPGA can write 33K*31 data to FIFO. From the
change of /HF signal(/HF: 1->0),I know it is successful. And i write a
DSP program that read data from Xbus by DMA. But the DMA never happen.
I have checken the registers of DAM and Xbus,all are right.
I have read the SPRU190D and SPRA547A,bus still cannot solve this
trouble. Please give me some advice.
Thansk a lots.
Best regard

huguang
10/17/02 /* My program */
#include <std.h>
#include <c6x.h>
#include <csl.h>
#include <csl_irq.h>
#include <csl_timer.h>
#include <csl_xbus.h>
#include <csl_dma.h>

#define BUFFSZ 1024

#define MEM_SRC 0x7FF00000 /* Source address for transfer */

#define FALSE 0
#define TRUE 1 void timer0_init(void);
extern int flag=0;
int time_num=0;

extern int time_flag=0;
void set_interrupts(void);
void c_int14 (void);
extern far void vectors();
void set_interrupts_dma(void);

static Uint32 BuffA[BUFFSZ/sizeof(Uint32)];
static Uint32 BuffB[BUFFSZ/sizeof(Uint32)];

static DMA_Handle hDma;

volatile int transfer_done = FALSE;
static TIMER_Handle hTimer1;
static Uint32 TimerEventId;

XBUS_Config xbusCfg = {
0x00007000, /* Global Control Register(XBGC) */
0x00000000, /* XCE0 Space Control
Register(XCE0CTL) */
0x00000000, /* XCE1 Space Control
Register(XCE1CTL) */
0x00000000, /* XCE2 Space Control
Register(XCE2CTL) */
0x00000000, /* XCE3 Space Control FFF40302
Register(XCE3CTL) */
0x00000000, /* XBUS HPI Control
Register(XBHC) */
0x00000000, /* XBUS Internal Master Address
Register(XBIMA) */
0x00000000 /* XBUS External Address
Register(XBEA) */
}; void main()
{
int x;
Uint32 PriCtl,SecCtl,SrcAddr,DstAddr,XfrCnt;

CSL_init();

XBUS_config(&xbusCfg);

for (x=0; x<BUFFSZ/sizeof(Uint32); x++) {
BuffA[x] = 0x00000000;
BuffB[x] = x+1;
}

DMA_reset(INV);
hDma = DMA_open(DMA_CHA1,DMA_OPEN_RESET);

/* Generate discrete DMA parameters using 'make' macros */
PriCtl = DMA_PRICTL_RMK(
DMA_PRICTL_DSTRLD_NONE,
DMA_PRICTL_SRCRLD_NONE,
DMA_PRICTL_EMOD_NOHALT,
DMA_PRICTL_FS_DISABLE,
DMA_PRICTL_TCINT_ENABLE,
DMA_PRICTL_PRI_CPU,
DMA_PRICTL_WSYNC_NONE,
DMA_PRICTL_RSYNC_NONE,
DMA_PRICTL_INDEX_A,
DMA_PRICTL_CNTRLD_A,
DMA_PRICTL_SPLIT_DISABLE,
DMA_PRICTL_ESIZE_32BIT,
DMA_PRICTL_DSTDIR_INC,
DMA_PRICTL_SRCDIR_NONE,
DMA_PRICTL_START_STOP
);

SecCtl = DMA_SECCTL_RMK(
DMA_SECCTL_WSPOL_ACTIVEHIGH,
DMA_SECCTL_RSPOL_ACTIVEHIGH,
DMA_SECCTL_FSIG_NA,
DMA_SECCTL_DMACEN_LOW,
DMA_SECCTL_WSYNCCLR_NOTHING,
DMA_SECCTL_WSYNCSTAT_CLEAR,
DMA_SECCTL_RSYNCCLR_NOTHING,
DMA_SECCTL_RSYNCSTAT_CLEAR,
DMA_SECCTL_WDROPIE_DISABLE,
DMA_SECCTL_WDROPCOND_CLEAR,
DMA_SECCTL_RDROPIE_DISABLE,
DMA_SECCTL_RDROPCOND_CLEAR,
DMA_SECCTL_BLOCKIE_ENABLE,
DMA_SECCTL_BLOCKCOND_CLEAR,
DMA_SECCTL_LASTIE_DISABLE,
DMA_SECCTL_LASTCOND_CLEAR,
DMA_SECCTL_FRAMEIE_DISABLE,
DMA_SECCTL_FRAMECOND_CLEAR,
DMA_SECCTL_SXIE_DISABLE,
DMA_SECCTL_SXCOND_CLEAR
);

SrcAddr = (Uint32)MEM_SRC;
DstAddr = (Uint32)BuffA;
XfrCnt = DMA_XFRCNT_RMK(
DMA_XFRCNT_FRMCNT_OF(0),
DMA_XFRCNT_ELECNT_OF(BUFFSZ/sizeof(Uint32))
);

/* Configure up the DMA channel */
DMA_configArgs(hDma,PriCtl,SecCtl,SrcAddr,DstAddr,XfrCnt);

set_interrupts_dma();

/* Start the DMA operation */
DMA_start(hDma);

while(1) {
};

}

void set_interrupts_dma(void)
{
IRQ_nmiEnable();
IRQ_globalEnable();
IRQ_disable(IRQ_EVT_DMAINT1);
IRQ_clear(IRQ_EVT_DMAINT1);
IRQ_enable(IRQ_EVT_DMAINT1);
return;
}

interrupt void c_int09(void)
{
transfer_done = TRUE;
return;
}


Reply by Jeff Brower ●October 18, 20022002-10-18
Hu Guang-

One thing I notice is that you mention "DSP program". The whole purpose of
C620x
Xbus is to transfer data to/from the chip at extremely high rates using onchip
DMA.
DSP code should not be involved, other than to initialize C602x registers for a
DSP-as-master transaction -- and even that can be performed by the host by
initializing those same registers using a few short Host-as-master transactions.

You should provide some more details on your setup. Are you in synchronous
mode?
What are the data bus values that you use at reset time to initialize basic
parameters, such as endianness, Xbus mode, etc? Have you put a logic analyzer
on the
address and data bus and control strobes? For some excellent examples of what
you
should see on the LA, look here:

http://www.signalogic.com/index.pl?page=logic

Jeff Brower
DSP sw/hw engineer
Signalogic hu guang wrote:
>
> Dear friend:
> Hi, i know there are many experts on DSP in the discussion group.
> Now i get a hard problem. I hope you can give me some advice and help.
> We design a DSP and FPGA system,with a FIFO to connect both.
> DSP: TMS320C6203
> FPGA: XILINX Vertex XC2V3000
> FIFO: IDT 72V36100, synchronous 64K*32
> FPGA writes data to FIFO,and DSP reads data form FIFO by Expansion Bus(Xbus).
> I has writen a HDL program ,so FPGA can write 33K*31 data to FIFO. From the
> change of /HF signal(/HF: 1->0),I know it is successful. And i write a
> DSP program that read data from Xbus by DMA. But the DMA never happen.
> I have checken the registers of DAM and Xbus,all are right.
> I have read the SPRU190D and SPRA547A,bus still cannot solve this
> trouble. Please give me some advice.
> Thansk a lots.
> Best regard
>
> huguang
> 10/17/02 > /* My program */
> #include <std.h>
> #include <c6x.h>
> #include <csl.h>
> #include <csl_irq.h>
> #include <csl_timer.h>
> #include <csl_xbus.h>
> #include <csl_dma.h>
>
> #define BUFFSZ 1024
>
> #define MEM_SRC 0x7FF00000 /* Source address for transfer */
>
> #define FALSE 0
> #define TRUE 1 > void timer0_init(void);
> extern int flag=0;
> int time_num=0;
>
> extern int time_flag=0;
> void set_interrupts(void);
> void c_int14 (void);
> extern far void vectors();
> void set_interrupts_dma(void);
>
> static Uint32 BuffA[BUFFSZ/sizeof(Uint32)];
> static Uint32 BuffB[BUFFSZ/sizeof(Uint32)];
>
> static DMA_Handle hDma;
>
> volatile int transfer_done = FALSE;
> static TIMER_Handle hTimer1;
> static Uint32 TimerEventId;
>
> XBUS_Config xbusCfg = {
> 0x00007000, /* Global Control Register(XBGC) */
> 0x00000000, /* XCE0 Space Control
> Register(XCE0CTL) */
> 0x00000000, /* XCE1 Space Control
> Register(XCE1CTL) */
> 0x00000000, /* XCE2 Space Control
> Register(XCE2CTL) */
> 0x00000000, /* XCE3 Space Control FFF40302
> Register(XCE3CTL) */
> 0x00000000, /* XBUS HPI Control
> Register(XBHC) */
> 0x00000000, /* XBUS Internal Master Address
> Register(XBIMA) */
> 0x00000000 /* XBUS External Address
> Register(XBEA) */
> };
>
> void main()
> {
> int x;
> Uint32 PriCtl,SecCtl,SrcAddr,DstAddr,XfrCnt;
>
> CSL_init();
>
> XBUS_config(&xbusCfg);
>
> for (x=0; x<BUFFSZ/sizeof(Uint32); x++) {
> BuffA[x] = 0x00000000;
> BuffB[x] = x+1;
> }
>
> DMA_reset(INV);
> hDma = DMA_open(DMA_CHA1,DMA_OPEN_RESET);
>
> /* Generate discrete DMA parameters using 'make' macros */
> PriCtl = DMA_PRICTL_RMK(
> DMA_PRICTL_DSTRLD_NONE,
> DMA_PRICTL_SRCRLD_NONE,
> DMA_PRICTL_EMOD_NOHALT,
> DMA_PRICTL_FS_DISABLE,
> DMA_PRICTL_TCINT_ENABLE,
> DMA_PRICTL_PRI_CPU,
> DMA_PRICTL_WSYNC_NONE,
> DMA_PRICTL_RSYNC_NONE,
> DMA_PRICTL_INDEX_A,
> DMA_PRICTL_CNTRLD_A,
> DMA_PRICTL_SPLIT_DISABLE,
> DMA_PRICTL_ESIZE_32BIT,
> DMA_PRICTL_DSTDIR_INC,
> DMA_PRICTL_SRCDIR_NONE,
> DMA_PRICTL_START_STOP
> );
>
> SecCtl = DMA_SECCTL_RMK(
> DMA_SECCTL_WSPOL_ACTIVEHIGH,
> DMA_SECCTL_RSPOL_ACTIVEHIGH,
> DMA_SECCTL_FSIG_NA,
> DMA_SECCTL_DMACEN_LOW,
> DMA_SECCTL_WSYNCCLR_NOTHING,
> DMA_SECCTL_WSYNCSTAT_CLEAR,
> DMA_SECCTL_RSYNCCLR_NOTHING,
> DMA_SECCTL_RSYNCSTAT_CLEAR,
> DMA_SECCTL_WDROPIE_DISABLE,
> DMA_SECCTL_WDROPCOND_CLEAR,
> DMA_SECCTL_RDROPIE_DISABLE,
> DMA_SECCTL_RDROPCOND_CLEAR,
> DMA_SECCTL_BLOCKIE_ENABLE,
> DMA_SECCTL_BLOCKCOND_CLEAR,
> DMA_SECCTL_LASTIE_DISABLE,
> DMA_SECCTL_LASTCOND_CLEAR,
> DMA_SECCTL_FRAMEIE_DISABLE,
> DMA_SECCTL_FRAMECOND_CLEAR,
> DMA_SECCTL_SXIE_DISABLE,
> DMA_SECCTL_SXCOND_CLEAR
> );
>
> SrcAddr = (Uint32)MEM_SRC;
> DstAddr = (Uint32)BuffA;
> XfrCnt = DMA_XFRCNT_RMK(
> DMA_XFRCNT_FRMCNT_OF(0),
> DMA_XFRCNT_ELECNT_OF(BUFFSZ/sizeof(Uint32))
> );
>
> /* Configure up the DMA channel */
> DMA_configArgs(hDma,PriCtl,SecCtl,SrcAddr,DstAddr,XfrCnt);
>
> set_interrupts_dma();
>
> /* Start the DMA operation */
> DMA_start(hDma);
>
> while(1) {
> };
>
> }
>
> void set_interrupts_dma(void)
> {
> IRQ_nmiEnable();
> IRQ_globalEnable();
> IRQ_disable(IRQ_EVT_DMAINT1);
> IRQ_clear(IRQ_EVT_DMAINT1);
> IRQ_enable(IRQ_EVT_DMAINT1);
> return;
> }
>
> interrupt void c_int09(void)
> {
> transfer_done = TRUE;
> return;
> }