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Or a larger SDRAM? The largest one readily available that fits standard JEDEC site is 8M x 32, or 256 Mbit. -Jeff -------- Original Message -------- Subject: [c55x] 5502 EMIF / SDRAM Interface Date: Tue, 25 Jan 2005 10:29:19 -0600 From: Ryan Piwowarski <> To: TI documentation for the 5501/5502 EMIF (SPRU621D) suggests that it is compatable with 64Mbit SDRAM. That would be 2Mx32-bit or 8MB of data. The maximum CE space is only 4MB. So, is it actually possible to interface a 64Mbit SDRAM to a single CE and yet still address all of it? Can a single SDRAM chips span multiple CE's? |
[Fwd: 5502 EMIF / SDRAM Interface]
Started by ●January 25, 2005
