Lost Secrets of the H-Bridge, Part V: Gate Drives for Dummies

Jason SachsJune 22, 20241 comment

Today we’re going to talk about gate drive circuits for MOSFETs and IGBTs. But first I want to share a story.

Magic smoke

About 25 years ago, I shared an office with a nice guy named Larry who was working on a linear actuator, which was basically just a brushed DC motor connected to a lead screw. Larry had an easy job in some ways, and a tough job in others.

The easy part was that it was just an on-off system. No pulse-width modulation. The DC motor was driven electrically with an H-bridge. Somebody flipped a switch somewhere, and Larry’s board had a microcontroller (a PIC16C74 if I remember it correctly) which turned the MOSFETs on or off, so that either the motor was connected across the DC link voltage, or it was connected in reverse, or it was left open-circuited with diodes to conduct the freewheeling current.

The hard part was that the DC link could vary anywhere between 50V and 100V, which was kind of a pain to deal with, for a number of reasons. A 100V MOSFET wouldn’t cut it — no design margin — and at the time, 150V MOSFETs were relatively new, and not particularly common or cost-effective, so I’m pretty sure he used an International Rectifier IRL640, which was a logic-level (5V) 200V MOSFET. IR’s “Fifth-Generation HEXFETs” with an “N” suffix (for example, the IRF530N with better on-resistance specifications than the older third-generation equivalent IRF530) were just starting to be introduced around 1998 into their 100V and lower-voltage MOSFETs, but even in 1999 they had not yet made inroads in the 200V series of MOSFETs. (The regular non-logic-level IRF640N came out around October 2000.) I’m not sure IR ever made an IRL640N; they sold some of their product line to Vishay in 2006-2007 as part of a management takeover, and the equivalent part nowadays would be the Vishay IRL640. If you want to see the original IR datasheet you have to download it from one of the archiving websites like datasheetcatalog.com and trust that they got the latest version.

Anyway, Larry had a working prototype, and it worked well, except occasionally one of the MOSFETs went pop! and let out its magic smoke. Larry would diligently replace the offending transistor with a new one, and go on testing his design. After about the ninth or tenth part replacement, I think someone noticed, and one of the project managers probably cajoled him into believing something just might be wrong with the design, so perhaps he should get another pair of eyes looking at it. I was still fairly green as an engineer, and up to my eyeballs in a battery charger design, but another coworker gave him a hand and figured out what was going on.

The short answer is that Larry’s design had the potential every now and then to cause shoot-through in one half-bridge leg of the H-bridge. Larry’s microcontroller code would turn on one of the MOSFETs — let’s say it’s QAH. The gate drive for QAH would turn on, and the voltage across that transistor would rapidly decrease. This would cause the voltage across the complementary transistor, QAL, to rise rapidly — remember, the total voltage across both transistors is the DC link voltage, which remains essentially the same — and the parasitic capacitance between gate and drain would cause QAL’s gate voltage to rise just enough to turn it on partially, so current flowed directly through both QAH and QAL for a short time, until QAL’s gate drive pulled the gate back down again. If you want to read about this phenomenon, IR created a decent white paper about it.

The longer answer involves some discussion of what’s important in a gate drive circuit. And hence we have Part V to our series.

A quick recap, and some sympathy for Alaska and Hawaii

Wow, I feel like Rip Van Winkle — it feels like just yesterday that I had written a series of articles on H-bridges, and was in the middle of this fifth installment, when I got distracted… and now ten years have gone by. In the past decade, International Rectifier was acquired by Infineon in 2015, and the silicon carbide (SiC) and gallium nitride (GaN) transistor markets have exploded from niche high-performance solutions to core enablers in electric vehicles and high-efficiency power conversion.

Here are those first four articles from 2013 and 2014:

We went into a lot of detailed mathematical discussion about what happens in an H-bridge under pulse-width modulation.

This article’s a little different. (I have debated publishing it; in the intervening years since I finished Part IV, the Indiana Jones franchise has come out with a fifth movie, and look where that got them.) But this one will have fewer equations. And you probably won’t want to hear some of the things I’m going to say: one of which is don’t design your own gate drive circuit with discrete components. Use an off-the-shelf IC. Oh, except that in many cases off-the-shelf IC’s aren’t good enough either, at least not without some supplementary circuit components to tune or boost their performance. Probably not what you were expecting to hear.

The other reason you won’t want to hear some of the things I’m going to say, is that nobody really wants to spend time on gate drive design. It’s a necessary evil. We all want to be doing great things in a microprocessor, nifty algorithms to control motors and do all sorts of fun stuff. At the end of the day, we just want to output PWM waveforms and have those transistors switch on and off accordingly. (Simon says turn on! Simon says turn off! Turn on! Ah – Simon didn’t say! Ha-ha!) Why can’t those darned transistors just do what we want? Well, we have to add extra circuitry to do that.

Once upon a time, I wrote an article (Byte and Switch, Part I) about how to drive an N-channel MOSFET from a microcontroller. Not too bad, just a resistor or two. With a half-bridge or an H-bridge, on the other hand, we have to manage those upper transistors, and anyway we really want the lower transistors to turn on and off more quickly than we can do with just a resistor from a microcontroller pin. But it’s the upper transistors that are a pain. Because for almost any practical half-bridge circuit, we’re going to use N-channel transistors (and I’ve written about why that is in another article), which means we need to have a gate drive circuit that applies a voltage relative to the upper transistor’s source terminal, which is the output terminal — VA in the diagram above — that’s going up and down between DC link terminals. It’s generally at a high voltage (relatively speaking, at least from the standpoint of a microcontroller) and is going up and down, and that’s a pain to deal with.

It makes me think of what our neighbors in Alaska and Hawaii must deal with, when it comes to buying things the rest of us Americans take for granted. Because I’m sure that a lot of people that sell stuff in the continental USA just don’t think about how to get their products from point A to point B, and it’s a pain to get it sent across the ocean. Why should they have to worry about taking the extra effort, just to support another 1% of their fellow citizens? They just want to sell stuff. If the regular low-cost delivery truck approach won’t work, either it costs a lot more, or your attempt to get it will fail altogether.

So it is with gate drive circuits. It’s going to take some extra cost and/or effort to get it done, more than your typical op-amp or digital logic circuit. If you don’t want to pay much, you’ll have to know what you’re doing and be willing to take the time. Or you can pay to let someone else do it — someone who knows what they’re doing. Personally, I’d take that route. Find the Power Electronics Guru, let him worry about the gate drives, and then you can go play with control algorithms or whatever it is you actually care about.

But you’re still reading....

So what is important about a gate drive circuit?

Here’s a list of things you should be aware of:

  • How transistors behave
  • What happens when they switch on and off
  • What datasheet specifications determine how fast they turn on and off
  • How fast they should switch on and off
  • How to select a gate driver IC
  • What additional circuitry is needed with the gate driver IC
  • What supply voltage to use with the gate driver IC
  • How to supply voltage to the gate drive circuit of upper transistors
  • What makes a good circuit board layout
  • What can cause failures
  • How big a deal is a power electronics failure, anyway?

I will not cover all of these extensively — and I’ll just barely touch on the layout issue — but you should know enough about each of these to appreciate when you’re in over your head. There is a big difference between designing gate drive circuitry for a 24V 100W power stage and a 400V 10kW power stage. (Hint: learn on the small low-voltage stuff.) OSHA has an electrical safety acronym, BE SAFE:

  • Burns
  • Electrocution
  • Shock
  • Arc flash/blast
  • Fire
  • Explosions

All of these things can happen when electrical components fail. Usually transistors stop working because they overheat due to excessive power dissipation, which in turn is caused either by high current flowing for too long (I²R dissipation), or not switching fast enough (V × I for too long), or voltage breakdown causing uncontrolled current. If you’re lucky, the transistors just let the magic smoke out and that’s it — your system just stops working. If you’re not, there can be arc discharge, fire, or explosions (“rapid disassembly”) due to the transistor failure or other components like capacitors, magnetics, and even circuit board traces. The capacitor failures are the scary ones, and there are a number of exploding capacitor videos out there, to give you an idea.

Treat electronics with respect!

Know Your Enemy: Transistors

The first thing we have to do is know what makes our transistors tick. And by the way, the switching devices of choice these days are MOSFETs and IGBTs. Power bipolar transistors don’t really get used much anymore (though if you have the misfortune of using them, Switching Power Supply Design by the late Abraham Pressman has some good coverage of bipolar transistor drive circuits). And the other solid-state switching devices, whether the tamer ones like SCRs and triacs, or the wilder ones like GTOs and MCTs and IGCTs — or whatever it is they’re trying to promote as high-power replacements to IGBTs — are too exotic from my point of view for me to be able to give you any useful advice.

MOSFETs and IGBTs are very similar to turn on and off, and we’ll see why shortly. They’re both voltage-controlled devices. Bipolar transistors are essentially current-controlled current regulators: current flowing from collector to emitter is an amplification of the current flowing into the base terminal. And that’s what makes them a pain. Nobody wants to have to put in 1A of current all of the time to get out 10A of current some of the time. Too much work. MOSFETs and IGBTs are voltage controlled current regulators: you apply 0V between gate and source (gate to emitter in an IGBT) and they are turned off; you apply a few volts between gate and source, and they want to conduct maybe 2A of current; you apply 12V between gate and source, and they want to conduct maybe 50A of current. This makes more sense if you look at the appropriate diagram in the IRL640 datasheet:

Oh, those quaint old plots. Let’s read the graph: what it says is that someone ran a characterization test on the IRL640, and found that 2.25V from gate to source (2.25Vgs) yields about 1A whether the drain-to-source voltage is 0.7V or 10V or 50V. With 3Vgs you get 10A. With 4Vgs you get about 30A. On the right side of the graph, you get constant current behavior. On the left side of the graph, with low drain-to-source voltages, the behavior is resistive. The resistive behavior is called the linear region, sometimes the ohmic region; the constant-current behavior is called the saturation region. Which is really confusing because it seems like it should be the other way around: what you generally want in a switching power converter is for the voltage across the switch to be as low as possible when it’s on, so the switch is saturated; but if the load is too low of an impedance, the voltage from drain to source will rise, and there will be a lot more power dissipation in the MOSFET, so it’s no longer acting as a switch but instead as a linear dissipation element. But the textbook terms are linear region for the resistive behavior, saturation region for constant-current behavior. Go figure.

I’ve highlighted the resistive/linear/ohmic region in green on another copy of this graph below, and the saturation/constant-current region in yellow-orange. (In between those regions, the MOSFET has intermediate behavior, with increases in current causing higher than linear increases in voltage.)

If you want the MOSFET to act like a switch, there are two ways of thinking about it, simply and strictly.

The simple way is to be in either of the following states, and not in between:

  • on: in the linear region (green area shown above), conducting current, with VGS large enough to minimize drain-to-source voltage
  • off: VGS small (near zero or below zero) to minimize the drain current to its leakage value (microamperes for most power MOSFETs) while withstanding the required drain-to-source voltage

It’s not an instantaneous process to get between these two states, and the transition depends on the load charateristics. As an example, suppose there is 5 A flowing through an inductive load and into the upper transistor’s body diode, with DC link at 50 V. As gate-to-source voltage increases, the voltage vs current curve follows the fuchsia curve, through a sequence at turn-on:

  • at VDS = 50 V, up from zero current through point A at 100 mA, at somewhere around VGS = 2.0 V
  • then from point A to point B to carry full load current of 5A at approximately VGS = 2.7 V
  • then from point B to point C as the drain-source voltage decreases across the switch
  • then from point C to point D as VGS increases to the required gate voltage.

We’ll look at some time-series waveforms that show this in just a bit.

The strict way of ensuring the MOSFET acts like a switch is a little more complicated, based on the characteristics listed in the datasheet.

  • When the switch needs to be on, you must apply at least the voltage required to achieve the specified resistance Rdson in the datasheet. For most MOSFETs, this is 10V; for logic level MOSFETs it is anywhere from 5V down to 1.8V, with fewer options the lower you go.
  • The load current must be low enough (less than the current specified in the Rdson section of the datasheet) that the resistive behavior of the MOSFET is possible. If the load impedance is too low, then the MOSFET may stop being resistive and act instead as a constant current element, with a significant portion of the load power being dissipated
  • When the switch needs to be off, you must keep the gate voltage Vgs below the threshold voltage, either at a negative voltage, or as close to 0 as possible.
  • There is an unavoidable transition between the off and on states when the power dissipation in the MOSFET is high — corresponding to the operating range between points A and B and C. You must minimize the time spent in transition. Typically this is 1 microsecond or less. (What? You have a 10 microsecond switching time? Ha, that’s funny, it made me laugh.)

Why would it take time to switch between on and off? Because there is unavoidable parasitic capacitance between both the gate and the drain and source terminals. Here’s Figure 6 from the IRL640 datasheet, showing gate-to-source voltage vs. gate charge:

This is classic MOSFET behavior. These curves have three sections, which I’ve labeled below as ① ② ③:

The leftmost section ① occurs when the MOSFET changes from the off-state into the constant current region, and is essentially constant capacitance with a large voltage across drain to source. At the right end of this section, the current in the MOSFET will increase — this corresponds to the change from point “A” to point B” in the Id vs Vds diagram I annotated earlier. Figure 6 shows a change in gate charge from about 0 to 5 nC from 0 to 3 V, so that’s \( C = \frac{\Delta Q}{\Delta V} \) = 5 nC / 3 V ≈ 1700 pF.

The middle section ② is a plateau, sometimes called the Miller plateau; in order to turn the MOSFET from an off state to an on state, you need to get the voltage across drain to source to decrease. (Point “B” to point “C”.) This involves discharging the gate-to-drain capacitance, by letting current flow out of the drain and into the gate. A large portion of the charge that needs to be provided to the gate is in this section. The gate voltage stays essentially constant in this region. Figure 6 shows this plateau voltage at about 3.2 – 3.5V for \( I_D = \) 17 A. The plateau voltage will be lower at lower load currents, but not that much lower; Figure 1 shows \( V_{gs} = \) 2.25 V at 1 A, and 3 V at 10 A, so the current capability really changes quite a lot with gate voltage.

Finally, once the gate-to-drain capacitance is discharged, then the gate voltage can increase further, so the rightmost section ③ involves providing enough additional charge to bring the gate voltage up to the voltage listed in the datasheet to achieve the desired Rdson — 5V in case of the IRL640. (Point “C” to point “D”.) Figure 6 shows a change in gate charge from about 35 nC to 60 nC to get from 4 V to 7 V on the gate, so that’s \( C = \frac{\Delta Q}{\Delta V} \) = 25 nC / 3 V ≈ 8300 pF.

Note that the gate-to-drain charge is almost independent of the DC link voltage: this datasheet shows three different voltages (40V, 100V, 160V) and the gate-to-drain charge changes only by about 10%. That’s because the capacitance is highly nonlinear, with a much higher capacitance at low drain-to-source voltages, and a much lower capacitance at high drain-to-source voltages. Maybe 10% of the gate charge is required to lower the drain-to-source voltage from 160V down to 40V, and the other 90% of the charge is required to bring it from 40V down to near zero. This is a good thing in many ways, because it means that the time needed for the MOSFET to switch its output voltage is very small, and if the bulk of the switching time is needed to go from 40V drain-to-source down to zero, that’s OK because the power dissipation is smaller.

The IRL640 datasheet even defines these three regions and specifies gate charge for each:

That’s a worst-case of 9 nC to get from \( V_{gs}=0 \) to the Miller plateau, another 38 nC to get through the Miller plateau, and a total of 66 nC to get to \( V_{gs}= \) 5 V where the MOSFET’s \( R_{dson} \) is fully specified.

How come the specs show 1800 pF typical input capacitance, when we came up with an estimate of 8300 pF from the upper part of the gate charge vs. voltage graph? 8300 pF does seem a little bit high, but if you look carefully, the specs are for 1800 pF at \( V_{ds} = \) 25V, whereas the upper part of the gate charge vs. voltage graph is when the transistor is fully on, and therefore \( V_{ds} = 0 \). Remember: nonlinear capacitance, that gets larger when the voltages are closer to zero. The 1800 pF typical input capacitance is pretty close to the 1700 pF we estimated from Figure 6 where the gate voltage is below the Miller plateau.

Switching time analysis

If you want to know what’s happening during the switching transients of the MOSFETs in a little more detail, you can look at a set of time waveforms showing transistor current \( I_{ds} \), drain-to-source voltage \( V_{ds} \), power dissipation \( P_{\rm diss} = I_{ds}V_{ds} \), and gate-to-source voltage \( V_{gs} \) — I’ll call this the “switching sequence diagram”:

Switching sequence diagram

These are typical waveforms for an inductive load where current \( I_1 \) is flowing through the load inductance. Real-world waveforms have more nonlinearity than I’ve shown here, and depend on body diode reverse-recovery, but as a first approximation, turn-on and turn-off transients for \( I_1 > 0 \) (positive currents) go somewhat like this:

  • \( t_1 \) — this is the time for the gate to charge up until \( V_{gs} \) reaches some threshold \( V_{GS1} \) where the current is significant. We can decide what “significant” is, but think of it as the current you start to care about during a switching transient, if it flows through both switching devices in a half-bridge, sort of a weak shoot-through. Maybe it’s 200 mA? Maybe it’s 500 mA? This might seem high, but since this time interval is likely to be less than a microsecond, it doesn’t matter so much. For the IRL640, this voltage is likely somewhere around 1.5 - 2.2 V, which we can measure with a couple of multimeters, or estimate from the spec or some of the characterization diagrams. (See below, VG(th) spec and figures 1 and 3) It’s going to be slightly higher than the so-called “gate threshold” voltage VG(th) in the spec, which is typically measured at 250 μA or 1 mA. The \( V_{gs} \) waveform is an exponential rise towards the gate drive power supply voltage \( V_{g0} \).

  • \( t_2 \) — this is the time for the gate to charge up until \( V_{gs} \) reaches some threshold \( V_{GS2} > V_{GS1} \) where the current \( I_{ds} = I_1 \). In our IRL640 example, it might be 2.0 - 2.5 V for \( I_1 = \) 5 A. During this interval, load current shifts from the other transistor in the half-bridge to this transistor. But the voltage across the transistor is still the full DC link voltage \( V_{dc} \), and at the end of this interval, power dissipation in the transistor reaches its maximum \( I_1V_{dc} \). Slower than the exponential rise in \( t_1 \) because some of the drive voltage \( V_{g0} \) is taken up by the voltage across the source inductance \( L_S \frac{dI}{dt} \) — see my recent article Turn It On Again: Modeling Power MOSFET Turn-On Dependence on Source Inductance

  • \( t_3 \) — now that this transistor is carrying the full load current, the drain-to-source voltage can drop. Gate charge continues to rise but gate-to-source voltage stays roughly constant (this is region ②, the Miller plateau) at \( V_{GS2} \). During this interval, load current shifts from the other transistor in the half-bridge to this transistor. But the voltage across the transistor is still the full DC link voltage \( V_{dc} \), and at the end of this interval, power dissipation in the transistor reaches its maximum \( I_1V_{dc} \). At the end of this interval, \( V_{ds} = I_1R_{dson} \) — we have reached the ohmic region of the transistor, where it behaves like a resistor. The value of \( R_{dson} \) will be higher than the spec at full turn-on; Figure 1 of the IRL640 seems to show about a factor of 2 between the resistance of \( V_{gs} = \) 2.25 V and the fully-specified turn-on at \( V_{gs} = \) 4.0 V.

  • \( t_4 \) — once the drain-source voltage has dropped to its minimum value, the gate voltage can continue to rise, allowing the resistance to drop to its fully-specified value once the gate voltages reaches the \( V_{gon} \), the gate voltage in the datasheet required for the specified resistance \( R_{dson} \). This time isn’t too critical as long as it’s a small portion of the switching period.

Time \( t_1 \) is the turn-on delay time (excluding propagation delays in the gate drive IC itself) and time \( t_2 + t_3 \) is the turn-on switching time. If we don’t want the transistor to blow up, it’s to our advantage to keep intervals \( t_2 \) and \( t_3 \) short; switching loss during the turn-on time is approximately \( E_{\rm on} = \frac{1}{2}(t_2+t_3)I_1V_{dc} \); this is an energy, measured in joules, occurring once each switching period.

Turn-off follows a similar sequence, but in reverse:

  • \( t_5 \) — we have to pull charge out of the gate until the gate voltage reaches the threshold \( V_{GS2} \).

  • \( t_6 \) — during the Miller plateau of turn-off, drain voltage rises to \( V_{dc} \).

  • \( t_7 \) — transistor current drops as gate voltage continues to fall, reaching the threshold \( V_{GS1} \).

  • After \( t_7 \), the gate voltage continues to fall towards zero, but we don’t really care about it since the transistor current is not significant.

Time \( t_5 \) is the turn-off delay time (excluding propagation delays in the gate drive IC itself) and time \( t_6 + t_7 \) is the turn-off switching time. Turn-off energy is approximately \( E_{\rm off} = \frac{1}{2}(t_6+t_7)I_1V_{dc} \)

These are real effects, by the way; measured oscilloscope waveforms are hard to find for some reason — you’d think the power semiconductor companies would include real waveforms in their appnotes — but with the flurry of technical papers on SiC MOSFETs in the 2010s, I found a few of them. The waveforms have some high-frequency resonances that I won’t go into, and the current overshoots a little due to diode reverse recovery, which I’m going to handwave away for the moment. But here they are, the same basic sequence:

Understanding this sequence is all you really need to analyze turn-off time, turn-on time, dead time, and switching losses. Dead time is the time you need between starting interval \( t_5 \) of one transistor in the half-bridge and starting interval \( t_1 \) of the complementary transistor; all you have to make sure is that interval \( t_2 \) of that other transistor doesn’t start until interval \( t_7 \) is complete, otherwise there will be significant shoot-through current.

The other information you need, aside from estimating the gate voltages \( V_{GS1}, V_{GS2}, V_{gon} \) shown in the switching sequence diagram, and the gate charge values, is the gate drive output characteristics (current and resistance), so you can figure out how long each interval lasts; for the most part the gate voltage rise and fall curves can be approximated by exponential behavior.

In this article, we’ll give some very rough calculations a little bit later, to give you an idea of how this works, but I’m not going to give a detailed numerical example of switching analysis, just to keep things short. I may do that in a future article, but for now I’ll just steer you towards Vishay’s Application Note AN608A, Power MOSFET Basics: Understanding Gate Charge and Using it to Assess Switching Performance.


An IGBT is very similar to a MOSFET in a lot of ways. It essentially looks like a combination of a MOSFET and a PNP bipolar power transistor:

The MOSFET is there to make this a nice voltage-controlled device, and it conducts the base current of the PNP. The PNP power transistor carries the bulk of the current.

When IGBTs are turned on, they look like a constant voltage drop (with maybe a little incremental resistance), typically in the 1.5-3.0V range. They need more voltage, typically 15V, to guarantee a good solid on-state. They take longer to switch and have this undesirable behavioral quirk called the “long tail” where it takes a while to turn them completely off — so if you’re switching off 5A in an IGBT maybe you can bring the current down from 5A to 0.5A in 50 nanoseconds but it takes another 500 nanoseconds to go from 0.5A to zero current. A MOSFET might take 50 nanoseconds to switch off completely.

There are a few other gotchas with IGBTs that I won’t get into, like the fact that you really need to provide a negative gate-to-emitter voltage to ensure that the IGBT stays fully off, or that in some devices, the collector-emitter breakdown rating is reduced under certain circumstances, like in this obsolete IXYS IXSH30N60B2D1, where it’s rated at 600V… except when it isn’t:

Or this ON Semi FGD3245G2, a “450V” IGBT for ignition coils, which is a little more prone to breakdown if the gate resistor gets too large:

Newer IGBTs generally tout “square SOA” (safe operating area) and don’t have these issues, but you should read the fine print of the datasheet. This is beyond my familiarity level — but if you happen to live with a power electronics designer, try waking up at dawn sometime while they’re still sleeping, and whisper “second breakdown” or “dynamic latch-up” in their ear, and let me know what happens.

So why do we bother with IGBTs if MOSFETs are much quicker to switch? Because IGBTs are better in high-voltage situations. Yeah, you can buy 600V and 650V MOSFETs; Infineon has their “CoolMOS” line with on-resistances roughly around the 100 mΩ range, maybe a little lower. Run these things at 10A and you get a 1V drop across drain-to-source. Run them at 20A and you get a 2V drop across drain-to-source. Run them at 50A and you get a 5V drop across drain-to-source… and you won’t be able to keep them cool very long. Whereas an IGBT’s on-state voltage is roughly constant. You can buy 600V IGBTs and get a 2-3V drop across collector-to-emitter. Put more current in them, and the on-state voltage doesn’t really increase much. You can buy 1200V IGBTs, 1800V IGBTs on up to the 3000V range or more, and the collector-to-emitter voltage drop is still in the 2-3V range. The higher the voltage in your system, the more efficient the IGBTs are, because this on-voltage drop is a lower fraction of the total system voltage.

In the ten-year hiatus since I started writing this article, silicon carbide MOSFETs (SiC) have become much more readily available, and they outcompete some IGBT applications, especially where switching frequencies above 20kHz are required.

For the lower voltage tasks, MOSFETs are going to win, because their on-resistances are low enough that they can beat IGBTs.

Gate Driver Selection

Let’s get back to the circuitry you need in a gate drive. I hope you have taken my advice and decided to use a dedicated gate drive IC.


The next thing to know is that, in most cases, you have to put something between this chip and the MOSFET you are trying to drive:

My friend Shannon called these extra somethings “jewelry” — I’m going to adopt the term — and he never liked adding them to circuits. Diodes, resistors, capacitors… any little whatnot that doesn’t really serve a purpose except in rare occasions, and just costs extra.

The most common jewelry you’ll need to add to a gate drive circuit is a series resistor:

The main reason you have to add it is to control the turn-on and turn-off time. If you’re lucky, the source and sink current capability of the gate driver you’ve chosen is too high. I’m going to look at the MCP1401 as an example, and we’ll see if this looks fast enough for our purposes:

This driver is good for 0.5 A, and has maximum output resistance of 16Ω sink / 18Ω source.

Let’s say we ran it off 5 V, and just hooked it up directly (\( R_1=0 \)) to an IRL640. What would happen? Remember our specs on gate charge, and our estimate of gate capacitance below and above the Miller plateau; we’ll add some estimates for gate inductance \( L_G \), source inductance \( L_S \), and drain inductance \( L_D \) to them:

  • \( Q_{gs} \le \) 9 nC
  • \( Q_{gd} \le \) 38 nC
  • \( Q_{g} \le \) 66 nC
  • \( C_{GS} = \frac{\Delta Q}{\Delta V} \approx \) 1700 pF below the Miller plateau
  • \( C_{GS} = \frac{\Delta Q}{\Delta V} \approx \) 8300 pF above the Miller plateau
  • \( C_{DG} \approx \) 50 pF at \( V_{dc} = \) 60V (see Turn It On Again)
  • \( C_{DS} \approx \) 200 pF at \( V_{dc} = \) 60V (see Turn It On Again)
  • \( L_{G} = \) 20 nH (7.5 nH package capacitance, 12.5 nH circuit board capacitance — this is just a vague guess, but we see again that it’s not critical, just as we did in Turn It On Again)
  • \( L_{S} = \) 12 nH (7.5 nH package capacitance, 4.5 nH circuit board capacitance — this capacitance is critical, and you should try to minimize the circuit board capacitance as much as you can)
  • \( L_{D} = \) 15 nH (4.5 nH package capacitance, 10.5 nH circuit board capacitance — also a vague guess, but this capacitance is significant but not as critical as \( L_S \))

Just to remind you of the gate charge/discharge waveforms, here’s the gate voltage graph I showed earlier:

Suppose the gate thresholds are \( V_{th1}= \) 2.0V (from Figure 3 of the IRL640 datasheet, at around 200mA at 25°C) and the Miller plateau happens at \( V_{th2}= \) 2.7 V, which is around \( I_d = \) 5 A in Figure 1 of the IRL640 datasheet. The driver can source up to 0.5 A, but we’ve got 18Ω source resistance, and at \( V_P = \) 5V, the currents into the gate are:

  • 278 mA (= 5V / 18Ω) when the gate voltage is zero
  • 166 mA (= (5V - 2.0V) / 18Ω) at \( V_{th1} \)
  • 128 mA (= (5V - 2.7V) / 18Ω) at the Miller plateau.

To figure out \( t_1 \) and \( t_2 \), we use the equations from Turn It On Again. Here’s \( t_1 \):

$$\begin{align} \tau &\approx \tau_C + \tau_L \\ \tau_C &= (R_1 + R_G)C_{GS} = 18\Omega \times 1700 {\rm pF} \\ &= 30.6 {\rm ns} \\ \tau_L &= (L_G + L_S)/(R_1 + R_G) = 32 {\rm nH} / 18\Omega \\ &= 1.8 {\rm ns} \\ \tau &\approx 32.4 {\rm ns} \\ t_1 &= \tau \ln \frac{V_{g0}}{V_{g0}-V_{GS1}} \\ &= \tau \ln \frac{5}{5 - 2.0} \\ &= 16.6 {\rm ns} \end{align}$$

This is a fairly short time, and the effect of \( \tau_L \) on this time is fairly small.

For \( t_2 \) we have a quadratic equation:

$$\begin{align} 0 &= A(\Delta t)^2 + B\Delta t + C \\ A &= V_{g0} - (V_{GS1}+V_{GS2})/2 \\ B &= - L_S I_L - (R_1 + R_G)C_{GS}(V_{GS2} - V_{GS1})\\ C &= -(R_1 + R_G)C_{DG}L_DI_L \\ \Delta t &= \frac{-B + \sqrt{B^2 - 4AC}}{2A} \end{align}$$


  • \( A = \) 5 − 2.35 V = 2.65 V
  • \( B = \) - 12 nH × 5 A − 18Ω × 1700pF × 0.7 V = -81.4 nVs
  • \( C = \) - 18Ω × 50 pF × 15 nH × 5 A = -6.75 × 10-17 Vs²
  • \( t_2 = \Delta t = \) 31.5 ns

At the Miller plateau we have our gate drive providing 128 mA, charging up 38 nC, which will take \( t_3 = Q_{gd}/I = \) 297 ns.

Note that the bulk of the turn-on time is at the Miller plateau. This is fairly typical; you can’t neglect \( t_1 \) and \( t_2 \), but they’re probably going to be a minor part of the turn-on transient.

The rest of the gate charge will take a while since the current decreases as the gate voltage gets higher, and we’re only using \( V_{g0} = \) 5 V… but once we get past the Miller plateau we’ve turned the switch on to the ohmic region, and further gate voltage will lower the Rdson to its specified value.

If we used \( V_{g0} = \) 10 V, this would happen more quickly:

  • about 500 mA to start (10 V / 18 Ω = 555 mA, but that’s above the source current rating, so the output source transistor is likely to start in its saturation region, and then switch to ohmic behavior when the gate voltage rises a bit)
  • 444 mA (= (10 V - 2.0 V) / 18 Ω) at \( V_{GS1} \)
  • 406 mA (= (10 V - 2.7 V) / 18 Ω) at the Miller plateau \( V_{GS2} \)
  • \( t_1 = \) 32.4 ns × \( \ln \frac{10}{10 - 2.0} = \) 7.2 ns
  • \( t_2 = \) 11.4 ns (the value of \( A \) changed to 10V − (2+2.7)/2 = 7.65V, but \( B \) and \( C \) coefficients stayed the same)
  • \( Q_{gd} = \) 38 nC charged with 406 mA leads to \( t_3 = \) 94 ns
  • roughly exponential decay from \( V_{gs} = V_{GS2} = \) 2.7 V to \( V_{gon} = \) 5 V (asymptotically approaching \( V_{g0} = \) 10 V), taking roughly \( t_4 = RC \ln \frac{V_{g0} - V_{GS2}}{V_{g0} - V_{gon}} = \) 18 Ω × 8300 pF × ln 7.3/5 = 56 ns


  • at \( V_p = \) 5 V, we have \( t_1+t_2+t_3 \approx \) 345 ns to get past the Miller plateau, then asymptotically approaching 5V for the turn-on spec
  • at \( V_p = \) 10 V, we have \( t_1+t_2+t_3 \approx \) 113 ns to get past the Miller plateau, and another \( t_4 = \)56 ns to get to the \( V_{gs} = \) 5V turn-on spec.

OK, higher gate drive power supply voltage = faster turn-on.

What about turn-off? Here we have a 16 Ω max sink resistance to the GND pin, a little bit stronger than the source resistance to \( V_{g0} \) at the VDD pin.

At \( V_{g0} = \) 5V, the gate drive will decay roughly exponentially to the Miller plateau; at around 2.7V this takes \( t_5 = RC \ln \frac{V_{g0}}{V_{GS2}} = \) 16 Ω × 8300 pF × ln 5/2.7 = 82 ns.

Then we have a current of 2.7V / 16 Ω = 169 mA to get through the Miller plateau; 38 nC discharged with 169 mA takes \( t_6 = Q_{gd}/I = \) 225 ns.

To figure out \( t_7 \) we use the same equations as for \( t_3 \) but with \( A = (V_{GS1}+V_{GS2})/2 - 0 = \) 2.35 V, and the same equations for \( B \) and \( C \) as earlier, but with total resistance of 16 Ω:

  • \( B = \) - 12 nH × 5 A − 16Ω × 1700pF × 0.7 V = -79.0 nVs
  • \( C = \) - 16Ω × 50 pF × 15 nH × 5 A = -6.0 × 10-17 Vs²

giving \( t_7 \approx \) 34.4 ns.

At \( V_{g0} = \) 10V, the time to decay to the Miller plateau increases to \( t_5 = \) 16 Ω × 8300 pF × ln 10/2.7 = 174 ns. The other times \( t_6 \) and \( t_7 \) are independent of \( V_{g0} \) and don’t change.

Total turn-off time:

  • at \( V_{g0} = \) 5 V: \( t_5 + t_6 + t_7 \approx \) 341 ns.

  • at \( V_{g0} = \) 10 V: \( t_5 + t_6 + t_7 \approx \) 433 ns.

Higher gate drive power supply voltage = slower turn-off, and determined mostly by \( t_5 = \) time to discharge down to the Miller plateau, and \( t_6 = \) time to cross the Miller plateau. Once we get past the Miller plateau, switching time is fairly quick.

Since this kind of calculation is something we might do repeatedly, I’ll give a Python class that will do it automatically:

import argparse
import numpy as np
import pandas as pd

Copyright 2024 Jason M. Sachs

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at


Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
See the License for the specific language governing permissions and
limitations under the License.

class GateDriveTimes(object):
    Calculates gate drive times, given parameters:
        Rgon, Rgoff   -- gate drive resistance during turnon/turnoff
        Vg0on, Vg0off -- gate drive voltage during turnon/turnoff
        (Rg and Vg0 are Thevenin equivalents of drive voltage)
        Vgs1          -- gate-source voltage of lowest significant transistor current
                         (typically in 50-250mA range)
        Vgs2          -- gate-source voltage at load current (Miller plateau)
        Vgon          -- gate-source voltage at specified Rdson
        Iload         -- load current
        Lg, Ls, Ld    -- parasitic series inductance at gate, source, drain
        Cgsoff        -- gate-source capacitance when transistor is off (Vds large)
        Cgson         -- gate-source capacitance when transistor is on (Vds near zero)
        Cgd           -- gate-drain capacitance when transistor is off (Vds large)
        Qgd           -- Miller charge
    Switching times t1-t7 are those as defined in  
    def __init__(self, params=None, **kwargs):
        p = {}
        if params is not None:
        self.params = argparse.Namespace(**p)
    def t1(self):
        p = self.params
        tau_C = p.Rgon * p.Cgsoff
        tau_L = (p.Lg + p.Ls)/p.Rgon
        return (tau_C + tau_L)*np.log(p.Vg0on/(p.Vg0on-p.Vgs1))
    def t2(self):
        p = self.params
        A = p.Vg0on - (p.Vgs1+p.Vgs2)/2
        B = -p.Ls*p.Iload - p.Rgon*p.Cgsoff*(p.Vgs2-p.Vgs1)
        C = -p.Rgon*p.Cgd*p.Ld*p.Iload
        return (-B + np.sqrt(B*B-4*A*C))/2/A
    def t3(self):
        p = self.params
        I = (p.Vg0on - p.Vgs2)/p.Rgon
        return p.Qgd / I
    def t4(self):
        p = self.params
        return p.Rgon*p.Cgson*np.log((p.Vg0on-p.Vgs2)/(p.Vg0on-p.Vgon))
    def t5(self):
        p = self.params
        return p.Rgoff*p.Cgson*np.log((p.Vg0on-p.Vg0off)/(p.Vgs2-p.Vg0off))
    def t6(self):
        p = self.params
        I = (p.Vgs2 - p.Vg0off)/p.Rgoff
        return p.Qgd / I
    def t7(self):
        p = self.params
        A = (p.Vgs1+p.Vgs2)/2 - p.Vg0off
        B = -p.Ls*p.Iload - p.Rgoff*p.Cgsoff*(p.Vgs2-p.Vgs1)
        C = -p.Rgoff*p.Cgd*p.Ld*p.Iload
        return (-B + np.sqrt(B*B-4*A*C))/2/A    
    def array(self):
        return np.array([self.t1, self.t2, self.t3, self.t4,
                         self.t5, self.t6, self.t7])
    def series(self):
        t1, t2, t3, t4, t5, t6, t7 = self.array
        return pd.Series(dict(
                         t1=t1, ton_delay=t1,
                         t2=t2, t3=t3, ton_switch=t2+t3,
                         t5=t5, toff_delay=t5,
                         t6=t6, t7=t7, toff_switch=t6+t7,

gdt = GateDriveTimes(Rgon=18, Rgoff=16,
                     Vg0on=5.001, Vg0off=0,
                     Vgs1=2.0, Vgs2=2.7, Vgon=5,
                     Lg=20e-9, Ls=12e-9, Ld=15e-9,
                     Cgsoff=1700e-12, Cgson=8300e-12,
gdt.series.map(lambda t: '%.2f ns' % (t*1e9))
t1               16.54 ns
ton_delay        16.54 ns
t2               31.52 ns
t3              297.26 ns
ton_switch      328.78 ns
ton_total       345.32 ns
t4             1156.52 ns
t5               81.86 ns
toff_delay       81.86 ns
t6              225.19 ns
t7               34.38 ns
toff_switch     259.56 ns
toff_total      341.42 ns
dtype: object
# now for 10V
gdt10 = GateDriveTimes(params=gdt.params, Vg0on=10)
gdt10.series.map(lambda t: '%.2f ns' % (t*1e9))
t1               7.22 ns
ton_delay        7.22 ns
t2              11.42 ns
t3              93.70 ns
ton_switch     105.11 ns
ton_total      112.34 ns
t4              56.54 ns
t5             173.88 ns
toff_delay     173.88 ns
t6             225.19 ns
t7              34.38 ns
toff_switch    259.56 ns
toff_total     433.44 ns
dtype: object
# now for 10V and 10A instead of 5A
gdt10 = GateDriveTimes(params=gdt.params, Vg0on=10, Iload=10)
gdt10.series.map(lambda t: '%.2f ns' % (t*1e9))
t1               7.22 ns
ton_delay        7.22 ns
t2              19.40 ns
t3              93.70 ns
ton_switch     113.09 ns
ton_total      120.32 ns
t4              56.54 ns
t5             173.88 ns
toff_delay     173.88 ns
t6             225.19 ns
t7              60.02 ns
toff_switch    285.20 ns
toff_total     459.08 ns
dtype: object

Easy peasy! (Although again, this is just an approximation, and you should validate it by measuring your circuit with an oscilloscope.)

Note that when the supply voltage increased, it shortened \( t_1, t_2, t_3, t_4 \) quite a bit (faster turn on times) but lengthened the turn-off delay \( t_5 \); turn-off switching time \( t_6+t_7 \) stayed the same. And when we increased the load current, times \( t_2 \) (turn-on ramp-up of current) and \( t_7 \) (turn-off ramp-down of current) increased but everything else stayed the same.

Are we good? All these turn-on and turn-off times are under a microsecond, so that’s good enough, right?

How fast is fast enough? How fast is too fast?

There are a bunch of reasons to want faster or slower turn-on or turn-off time, some of which conflict:

  • Faster turn-on and turn-off time is better, to lower the switching loss (reduce \( t_2 + t_3 \) and \( t_6 + t_7 \))
  • Faster turn-on and turn-off time in power MOSFETs avoids the risk of thermal runaway while the MOSFET is in the linear mode (secondary breakdown a.k.a. the Spirito Effect) — although in practice I wouldn’t expect to see this unless the turn-on and turn-off are very slow, at least in the tens or hundreds of microseconds range; check your MOSFET datasheet for the SOA curves. Below are a few parts that show this issue, clockwise from upper left: Infineon IPD033N06N, ST STL160N10F8, Nexperia BUK7J1R0-40H. The telltale sign in these graphs is the steepening of the SOA pulse curves towards the right of the graph, as the drain-source voltage gets larger and current gets smaller. At high currents, the SOA curves should show constant power, but in long pulses, the current decreases faster than the voltage increases; for example, the IPD033N06N has a 1 ms pulse SOA limit of 60 A at Vds = 5 V (300 W, 0.3 J), but only about 0.45 A at Vds = 60V (27 W, 0.027 J).

  • Slower turn-on and turn-off time to reduce radiated and conducted emissions — these are fast high-power transients, so the larger \( \frac{\Delta I}{\Delta t} \) and \( \frac{\Delta V}{\Delta t} \) are, the larger the induced electromagnetic fields — and since V and I are determined mostly by fixed application requirements, the faster we switch, \( \Delta t \) gets smaller and emissions get larger. (Soft-switching techniques can lower noise by switching when there is zero voltage across or zero current through the transistors, but those are beyond the scope of this article.)
  • Slower turn-off reduces potential overvoltage conditions caused by the inductance between the transistor and the nearest source of DC link capacitance
  • Slower turn-on reduces switching loss caused by reverse recovery of the body diode in the complementary device. For example, let’s say you’ve got a DC link of 80 V, and 5 A flowing through the inductive load and the body diode of the upper transistor, and you turn on the lower transistor really fast, so that it tries to grab the 5 A away from the diode and put 80 V across the diode. It takes the diode some time to stop conducting and enter a reverse-biased “off’ state, and during this time it’s still conducting, causing current to flow across both the body diode of the upper transistor, and the lower transistor. Uh oh. (I’ll come back briefly to this issue later, after sweeping it under the rug for now.)
  • Slower turn-on reduces the capacitive coupling into the gate of the complementary transistor through its gate-drain capacitance. If the gate-to-source voltage of that other transistor creeps up enough for drain current to flow, you’re in trouble — this is sometimes called “spurious turn-on” and is the effect I talked about at the beginning of this article, with Larry and the linear actuator. But you’re better off with a low-impedance gate drive, which can keep this from becoming a problem, than you are trying to tiptoe around the issue by trying to slow down the turn-on time.

These last two are the two big double whammies of fast turn-on. Fast turn-off doesn’t have as many disadvantages.

In general, you want to make turn-on and turn-off time as small as possible without making other problems arise. Engineers working with DC/DC converters and switching frequencies in the hundreds of kilohertz or even megahertz have their work cut out for them. If you’re working with motor drives, like I do, and you’re only at 20 kHz switching frequency, these issues aren’t so bad except for the reverse recovery loss. From TI’s Fundamentals of MOSFET and IGBT Gate Driver Circuits:

When speed enhancement circuits are mentioned, designers exclusively consider circuits that speed-up the turn-off process of the MOSFET. The reason is that the turn-on speed is usually limited by the turn-off, or reverse recovery speed of the rectifier component in the power supply. As discussed with respect to the inductive clamped model in Figure 3, the turn-on of the MOSFET coincides with the turn-off of the rectifier diode. Therefore, the fastest switching action is determined by the reverse recovery characteristic of the diode, not by the strength of the gate drive circuit. In an optimum design the gate drive speed at turn-on is matched to the diode switching characteristic.

So in a motor drive, I generally want to see turn-on only about as fast I can without running into extra switching loss caused by diode reverse recovery, and turn-off reduced until the switching loss is small compared to turn-on losses.

But how do we choose the turn-on and turn-off times?

Selecting a gate driver with enough current source and sink capability is important — they can be pretty strong; for example, the TC4451 has 12 A drive capability — and in general, you’ll want to pick one with a little more drive current than you need, and use series resistance between the output and the gate to slow things down a little bit. The output resistance of the gate driver IC is also important; as we saw with the 500 mA MCP1401 and the IRL640, the limiting factor was almost completely the IC’s output resistance rather than its drive current capability.

That gives you one design parameter you can tweak, series resistance \( R_1 \), to adjust both the turn-on time and the turn-off time, but you can’t adjust them separately. And if you want faster turn-off time than turn-on time, this is difficult to do with just a resistor.

Gate drive diode

The next level of gate drive jewelry is a Schottky diode to speed up turn-off time:

During the turn-on time, diode D1 is not forward-biased, and turn-on time is affected only by resistor \( R_2 \). During turn-off time, the diode is forward-biased and you get approximately the parallel combination of \( R_1 \) and \( R_2 \). Schottky diodes are a much better choice than “regular” PN junction diodes, for a couple of reasons:

  • Lower forward drop (at the cost of some reverse leakage current in the microampere or maybe low milliampere range, which doesn’t matter here, and even a diode rated at 20 V would work)
  • Fast response

They’re only a little bit more expensive than regular diodes, a few cents apiece at 1000-piece quantity. I’d probably pick a Nexperia PMEG2005CT, which is a pair of Schottky diodes each rated at a maximum of 390 mV voltage drop at 500mA, so in parallel that gets you 1 A capability with about 400 mV voltage drop.

I’m going to work with the MIC4104 as an example for the rest of this article, since it’s a half-bridge driver capable of driving two MOSFETs, and has a bit higher current and lower output resistance than the MCP1401. The MIC4014 has 3 A / 1.25 Ω sink, 2 A / 2.5 Ω source — my only trouble with this datasheet is that the typical sink/source resistances are in the “marketing” section, and not in the specs, at least not exactly:

You have to calculate output resistance yourself. The output voltage specs are 2.5 Ω (0.25 V at 100 mA) typical, 4.5 Ω maximum over temperature for the source current, but 1.125 Ω (0.18 V at 160 mA) typical sink for the low-side and 1.375 Ω (0.22 V at 160 mA) typical sink for the high side, 2.5 Ω maximum for both output sink currents.

Suppose I choose my external components as R1 = 2.5 Ω and R2 = 10 Ω and D1 = PMEG2005CT, both in parallel — what will I get for switching time?

I’m going to assume the worst-case numbers for the driver IC, namely Rsource = 4.5 Ω and Rsink = 2.5 Ω.

Total turn-on resistance is therefore Rsource + R2 = 14.5 Ω.

Total turn-off current depends on the output voltage, and is not simply a resistance, but we have several ways of modeling it, which I’ve covered in a recent article on modeling gate drive diodes. We can use a first-order linear approximation for the diode — \( V_D= \) 343 mV and \( R_D= \) 47.3 mΩ for the two parallel PMEG2005CT — and end up with a Thevenin equivalent:

  • \( V_{TH1} = \frac{R_2}{R_1+R_D+R_2}V_D = \) 273 mV
  • \( R_{TH1} = R_3 + ((R_1 + R_D) \parallel R_2) = \) 4.53 Ω total series resistance

(note \( R_3 = \) Rsink = 2.5Ω) — this Thevenin equivalent is valid as long as the gate voltage is above \( \frac{R_2+R_3}{R_2} V_D = \) 429 mV so that the current through the diode is positive. I’ll leave a more detailed discussion of why this approximation is appropriate in the Addenda for this article.

Right. Where were we? Oh yeah, calculating switching time!

Switching time with the turn-off diode

Just a reminder for the IRL260:

  • \( Q_{gs} \le \) 9 nC
  • \( Q_{gd} \le \) 38 nC
  • \( Q_{g} \le \) 66 nC
  • \( C_{gs} = \frac{\Delta Q}{\Delta V} \approx \) 1700 pF below the Miller plateau
  • \( C_{gs} = \frac{\Delta Q}{\Delta V} \approx \) 8300 pF above the Miller plateau

We assumed VGS1 ≈ 2V where current is just starting to be significant (50mA/100mA/200mA… whatever) and VGS2 ≈ 2.7V for Id = 5A, and Vgon = 5V.

For the MIC4104:

  • Q2p has Rdson ≤ 4.5 Ω maximum for sourcing current
  • Q2n has Rdson ≤ 2.5 Ω maximum for sinking current

We’ll calculate turn-on time (where the diode doesn’t do anything) based on resistor R2, and then turn-off time with and without the diode and resistor.

We’ll use the same R1 = 2.5 Ω and R2 = 10 Ω as earlier, with two parallel PMEG2005CT diodes modeled as a 0.343V + 47.3 mΩ resistor.

And I’ll use \( V_{g0} = V_P = \) 10V.

Now to calculate the switching times:

Copyright 2024 Jason M. Sachs

Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at


Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
See the License for the specific language governing permissions and
limitations under the License.

def switching_times(paramdict):
    p = paramdict
    R2 = p['R2']
    R1 = p['R1']
    Rdiode = p['Rdiode']
    Rgon = p['Rgsource'] + R2
    Rgoff1 = p['Rgsink'] + R2
    Rgoff2 = p['Rgsink'] + 1/(1/R2 + 1/(R1 + Rd))
    Vdiode = p['Vdiode']
    Vg0on = p['Vg0on']
    def calc_times(Rgoff, Vthoff):
        params = {}
        params['Vg0off'] = Vthoff
        params['Rgoff'] = Rgoff
        params['Rgon'] = Rgon
        return GateDriveTimes(**params).array
    rawtimes = np.array([calc_times(Rgoff,Vthoff)
                         for Rgoff,Vthoff in [(Rgoff1, 0),
                                             (Rgoff2, Vdiode*R2/(R2+R1+Rdiode))]]).T
    times = np.vstack([rawtimes[:4,:],
    return pd.DataFrame(times * 1e9,
                        index=['t1','t2','t3','t4','t2+t3','turnon total',
                               't5','t6','t7','t6+t7','turnoff total'],
                        columns=['Resistor only','Turn-off diode'])

df = switching_times(dict(Rgsource=4.5,
                          Vgs1 = 2.0,
                          Vgs2 = 2.7,
                          Vgon = 5.0,
                          Vg0on = 10,
                          Lg=20e-9, Ls=12e-9, Ld=15e-9,
                          Cgsoff = 1700e-12, Cgson = 8300e-12,
                          Cgd = 50e-12,
                          Qgd = 38e-9))
df.style.format('{:5.1f} ns')
  Resistor only Turn-off diode
t1 6.0 ns 6.0 ns
t2 10.8 ns 10.8 ns
t3 75.5 ns 75.5 ns
t4 45.5 ns 45.5 ns
t2+t3 86.2 ns 86.2 ns
turnon total 137.8 ns 137.8 ns
t5 135.8 ns 52.5 ns
t6 175.9 ns 71.3 ns
t7 32.5 ns 31.8 ns
t6+t7 208.4 ns 103.1 ns
turnoff total 344.2 ns 155.6 ns

You can see that adding the turn-off diode and resistor decreases the turn-off time to less than half of its original value, making the turn-on and turn-off times about equal. Aside from EMI there’s not really much downside to faster turn-off.

We could decrease turn-off time further by decreasing R1, or increase turn-on time by increasing R2, and try to optimize our switching times. But that kind of investigation is beyond the scope of this article.

The main point in selecting R1 and R2 is that you can choose the switching times independently:

  • select R2 to slow down turn-on time just enough to keep reverse recovery losses manageable and control the rate of voltage change dVds/dt during the Miller plateau
  • select R1 to manage turn-on time to minimize losses and keep the total pull-down resistance low — this helps prevent spurious turn-on when the complementary MOSFET is turned on, something that is much harder to do when you only have the one resistor.

Need Faster Turn-off? PNP to the Rescue!

Sometimes you need to speed up turn-off even further, and use an external transistor to pull current out of the gate faster, like in the circuit below:

Transistor Q3 will take the sink current from the gate driver and amplify it. Finding a good, fast, cheap PNP transistor may be tricky, though. An MMBT2907 is a decent SOT-23 PNP: DC current gain specified at 50 for a 500 mA collector current, and a gain-bandwidth product of at least 200 MHz. Several manufacturers make 2907 transistors in various packages. Or the slightly-more-exotic 2SA2016, with DC current gain of 200 at 500 mA and typical GBW of 290 MHz. These would help out if you were stuck using some wimpy gate drive IC with only 100 mA sink capability. But with today’s beefier gate drive ICs capable of sinking several amperes (the MIC4104 is good for sinking 3 A, for example), there’s less reason to use an external transistor.

What’s diode D1 for? Well, the one major weakness of an external PNP transistor is that you have to protect it from reverse-biasing; during turn-on, when you don’t care about Q3, the gate drive IC can yank its output upwards, and if Q3’s base gets pulled several volts above the emitter, then Q3 can get damaged. The MMBT2907A has an absolute max rating of -6 V for VEB. The diode keeps the base from rising above the emitter more than a diode drop.

Resistor R2 provides some pull-down resistance at low VGS, when the PNP transistor doesn’t have enough voltage to turn on. In some cases, R3 may be necessary to dampen oscillations that can occur with the interaction of the PNP transistor and the MOSFET.

I worked on a motor drive many years ago, where we used this circuit with the IR2136, and it did provide faster turn-off… which I guess doesn’t say much about that IR2136 as a gate driver.

The same approach is described in an appnote for the Silicon General SG1524B:

Highly capacitive loads such as presented by the gates of power MOSFET’s can be readily driven with the circuit in Figure 16. At turn-on, 200 mA of charging current [from the SG1524B’s output transistor] is conducted by D1. During turn-off D1 becomes back-biased by the pulldown resistor. Q1 turns on and provides 500 mA of discharge current.

The SG1524 was the first integrated PWM driver IC, designed by Bob Mammano in 1975, back in the heyday of bipolar power transistors in switch-mode converters. (Nearly fifty years later, you can still buy the SG1524; Silicon General, later renamed Linfinity, was purchased in 1999 by Microsemi, which in turn was acquired by Microchip in 2018.) Mammano’s appnote on this IC in the 1978 Silicon General Linear Integrated Circuits Product Catalog includes no mention of MOSFETs whatsoever, but suggests several topologies for driving external transistors. (“The availability of both collectors and emitters allows maximum versatility to enable driving either NPN or PNP external transistors....”) Maximum output current of the SG1524 was 100 mA — paltry by today’s standards — and the chip was more intended as a PWM controller. Hence the need for an external PNP like the one shown in Figure 16.

The appnote doesn’t say which transistor can be used for Q1, but it needs enough gain to get high current flowing through the emitter.

Old-school: Two pins are better than one?

The last variant of jewelry is just two resistors, independently setting turn-on and turn-off time — which you can get away with only when using a gate drive IC that has separate source and sink pins.

Ironically this was available from the SG1524 in the mid-1970s. By 1978, Silicon General had also designed the SG1627 dual high-current output driver, also with two separate collector-emitter pin pairs, capable of sourcing or sinking 500mA. The company’s 1984/85 General Product Catalog includes an application note showing the SG1627 used to drive a MOSFET in this separate source and sink topology:

Nowadays most gate drive ICs don’t have the separate source/sink pins — extra pins cost money and a larger package takes up more board space — but a few do, such as Infineon’s 1ED3431M, with its ON and OFF pins, shown here driving an IGBT:

Diode Reverse Recovery

Earlier I handwaved over the topic of diode reverse recovery, but I feel like I need to cover it at least enough to make the issue clear. Here’s our half-bridge again:

Suppose that current \( I_L = I_1 \) has been flowing through the body diode of, say, the lower transistor QAL for a while, and now we’re going to turn on the upper transistor QAH. Here’s the turn-on waveform:

Without diode reverse recovery, the current would commute from the lower diode (green waveform \( I_d \)) to the upper transistor (blue waveform \( I_{ds} \)) during time \( t_2 \), when the transistor is still in the saturation region.

Once the diode current reached zero, it would stop conducting and look like an open-circuit, with the reverse-bias voltage across the diode rising as the upper transistor drain-to-source voltage starts dropping.

Instead, the diode continues to act like a short-circuit for some time \( t_A \), conducting in the reverse direction until its current reaches some maximum value \( I_{rr} \). Then the diode finally gets a clue and the voltage across it starts rising, and the diode current drops until it hits zero after some time \( t_B \). The total reverse recovery time \( t_{rr} = t_A + t_B \), and the total reverse recovery charge \( Q_{rr} = \int I_{rr}\,dt \approx \frac{1}{2}t_{rr}I_{rr}. \)

This causes two issues:

  1. Turn-on time takes slightly larger; effectively, \( t_2 \) increases by \( t_A \). This is fairly minor.
  2. The reverse current through the diode flows across both devices, effectively dissipating extra energy \( E_{rr} = Q_{rr}V_{dc} \), mostly in the complementary MOSFET since it has to conduct higher current during the turn-on transient.

One major challenge is that the diode’s reverse recovery parameters (\( t_{rr}, I_{rr}, Q_{rr} \)) are not constant, but dependent on a number of conditions:

  • diode current before it turns off
  • rate of change of diode current during turn-off
  • diode junction temperature
  • reverse voltage applied across the diode

MOSFET datasheets will generally publish reverse recovery specifications at one data point, but that really doesn’t help you figure out the reverse recovery in your particular circuit. For example, here’s the specs on reverse recovery for the IRL640:

That’s \( t_{rr}= \) 470 ns max, \( Q_{rr} = \) 4.8 μC max, at 17 A, 100 A/μs, 25°C.

In the example we’ve been using, the current through the diode is 5 A, decreasing to zero in time \( t_2 = \) 10.8 ns, making dI/dt = 0.463 A/ns = 463 A/μs, at least if we believe that \( t_2 \) is reasonably accurate. This is nearly five times faster than the dI/dt used in the datasheet for reverse recovery, but the load current \( I_L \) is less than one-third of the value used in the datasheet for reverse recovery.

Aside from measuring the current and voltage waveforms in your circuit empirically, it’s going to be tough to make any conclusions about \( Q_{rr}, \) but we can at least get a sense the order of magnitude. ST’s AN5028 shows some graphs of reverse recovery charge vs. dI/dt:

Here if dI/dt changes by a factor of 20, from 20 A/μs to 400 A/μs, the reverse recovery charge increases by a factor of about 2.5. So we could just use the \( Q_{rr} \) from the datasheet with a fudge factor to accommodate uncertainty.

Just for some real numbers, suppose we used the IRL640 with a 60Vdc source across the half bridge, and with 5 A of current during turn on. Here’s the kind of losses we’d expect:

  • Conduction loss: Rdsonmax = 0.18 Ω, so I²Rdsonmax = 4.5 W
  • Turn-on loss, excluding reverse-recovery: \( E_{\rm on} = \frac{1}{2}(t_2+t_3)I_1V_{dc} = \) 0.5 × 86.2 ns × 5 A × 60 V = 12.9 μJ (= 0.26 W loss at 20kHz switching)
  • Turn-off loss: \( E_{\rm off} = \frac{1}{2}(t_6+t_7)I_1V_{dc} = \) 0.5 × 103.1 ns × 5 A × 60 V = 15.5 μJ if we use the Schottky diode and R1 = 2.5 Ω to speed up turn-off (= 0.31 W loss at 20kHz switching)
  • Diode reverse recovery: \( E_{rr} = Q_{rr}V_{dc} = \) 4.8 μC × 60 V = 288 μJ if we just use the value from the datasheet. (= 5.7 W loss at 20kHz switching)

Yow! That’s a lot, and it would be really suspicious for me to say don’t worry about reverse recovery in practice. Today’s MOSFETs seem to have body diodes with significantly lower reverse recovery than 20 years ago, in the hundreds of nanocoulombs — for example, look at Nexperia PSMN102-200Y, a 0.1 Ω 200V MOSFET with Qrr spec’d at 268 nC for 20 A, -100 A/μs. But if you want to make sure you’re not being hit with large power losses due to diode reverse recovery, measure it.

In this particular case it looks like we could slow down turn-on without causing much extra switching loss, and the slower we make turn-on, the lower dI/dt is and the less we have to worry about reverse recovery.

Which gate drive circuit is the best?

Unless you’re really lucky and a one-resistor solution just works, plan on having to adjust turn-on and turn-off time separately, which means using one of these solutions:

  • Gate drive IC with two output pins, connected to the gate with separate resistors
  • Gate drive IC with one output pin, and a Schottky diode and two separate resistors
  • Gate drive IC with one output pin, and some other internal mechanism to adjust turn-on and turn-off currents independently

The Schottky diode circuit is the most common approach that works with nearly any gate drive IC; the others are nice to have if your gate drive IC supports them.

Gate Drive Power Supply Management

There are a few more aspects of gate drives that I want to cover briefly. One is the management of power supplies for gate drives. This is one of the parts of gate drive design that no one likes. Everybody just wants to stick a perfect 10-volt source onto a gate drive IC and not worry about it, because that means the MOSFETs will be turning on perfectly to VGS = 10V and off to zero, right? Wrong.

Low-side gate drive supplies

The low-side gate drive is relatively easy to manage, or at least you’d think so. Voltage tolerance is one issue to deal with. If I want to turn a MOSFET on with 10 volts across its gate, then maybe I pick a voltage supply of \( V_{g0} = \) 12 V nominal, so that even at its worst-case, it is high enough to bring the MOSFET gate-to-source voltage to the specified 10 V within a reasonable amount of time. A 12V ± 5% supply ranges from 11.4 to 12.6V; these days you can find lots of fixed voltage regulators with 2% or 3% accuracy.

But this isn’t the end of the story; there are other reasons the MOSFET gate may not switch perfectly to the level you’d like:

  • Gate drive output stages don’t have enough bypass capacitance. Each time the MOSFETs QAH or QAL turn on, they require a relatively large amount of charge (typically nanocoulombs — the IRL640 needs a worst-case of 66 nC to turn it on completely, according to the datasheet) in a very fast time to turn on quickly. This means you really want to make sure there are good bypass capacitors right next to the gate drive IC, and that the MOSFET gate charge is only a small fraction of the charge stored in the bypass capacitor — I’d probably pick at least 1 μF, which means that the bypass capacitor charge Q = CV = 12 μC nominal for a 12 V nominal supply, and that’s 180× the 66nC gate charge of the IRL640. A 180:1 ratio of bypass capacitor charge to MOSFET gate charge may seem high, but you really do not want the voltage ripple of the gate drive power supply to eat into your error budget.

  • Voltage differences: The gate drive power supply reference isn’t at the same voltage as the MOSFET source. In some circuits, there is a sense resistor \( R_S \) between the MOSFET source and the DC link return voltage.

    In these circuits, \( R_S \) takes away some voltage that would be available for driving the MOSFET, and instead of your carefully controlled voltage \( V_{g0} \), you end up with an effective charging voltage \( V_{g0s} = V_{g0} - IR_S \), which will have a wider range. For example, if you need 10 V to turn QAL on fully, and \( R_S \) is going to see 1 V across it when current flows through QAL, then you need an 11 V power supply. When current is flowing the other way and there’s −1 V across \( R_S \), then the same 11 V power supply will deliver 12 V onto \( V_{GS} \) of QAL. Inductive spikes make this issue worse, lowering the available voltage when current through the transistor increases, and raising the available voltage when current through the transistor decreases. Adding a component in series also makes it more challenging to keep low source inductance in the circuit layout; I mentioned in Turn It On Again that this is a critical parameter, and more source inductance slows down the turn-on time.

Of these two issues, the voltage difference between MOSFET source and VSS is the trickier one. There’s not much you can do about it, aside from managing the series resistance and inductance as carefully as possible during circuit layout.

The more serious aspect of these voltage differences involves the turn-off transient. You might think the gate drive IC is trying to pull the MOSFET gate down to “zero”, but if there’s a voltage across \( R_S \), then it can add or subtract from the effective output voltage of the gate driver, depending on the direction of current. If current is flowing from drain-to-source through \( R_S \), the effective sink voltage will be slightly negative, and the MOSFET will switch off faster. If current is flowing from source-to-drain, the effective sink voltage will be slightly positive, and the MOSFET will take longer to turn off, or may not even completely turn off.

If you’re lucky, you can use a gate drive IC that has a separate pin for connecting to the lower MOSFET source, when you expect it to be significantly different from “ground” in your circuit; for example, the LF21814 has separate COM and VSS pins, allowing up to 5V difference between them:

Then the COM pin can be connected to the MOSFET source, and it’s not a big deal if there’s a small difference between VSS and COM as long as you meet the datasheet spec on this voltage difference. This can work very well for a single half-bridge circuit, but if you want to use an integrated H-bridge driver or three-phase bridge driver, you’re likely to find at most one COM pin, so this won’t help when there are voltage differences between the source terminals of two or three MOSFETs. In rare cases you will find dedicated pins for the source terminals in a multi-phase gate driver, like in the TI DRV8334 with its separate low-side source terminals SLA, SLB, SLC.

In the end, there’s a tradeoff:

  • Use a gate drive IC with dedicated return pins for the low-side MOSFET source(s) — this is more robust to voltage differences, and helps keeps the effective sink voltage stay closer to zero for MOSFET turn-off (= less variation in turn-off time), but there are fewer options in selecting ICs.
  • Use a gate drive IC without dedicated return pins for the low-side MOSFET source(s) — lots of options here, but you’ll have to tolerate voltage differences between MOSFET source and the VSS pin of the gate drive IC, which can cause wider variation in the turn-off time because of the variation in effective sink voltage. If these voltage differences are high enough, it can damage circuit components.

And either way, the effective drive voltage \( V_{g0s} = V_{g0} - IR_S \) for MOSFET turn-on will vary, depending on the source-to-VSS difference.

All this fuss about gate drive supply voltage gets even more interesting when you start looking at the high-side gate drives.

Bootstrap high-side gate drives

Somehow we have to turn the upper transistor on and off. This is a more difficult task than the low-side gate drive, since the upper transistor’s gate voltage must be controlled relative to its source voltage, which is moving up and down in voltage every time the transistors switch state.

Modern gate drive ICs will do this automatically for you, and you don’t have to worry about how they turn logic-level signals into drive signals for internal output MOSFETs that are zooming around to keep up with the transistor. A typical half-bridge driver looks like this circuit, where the grey box is the gate drive IC and everything else is the “jewelry”.

Then the only gotcha that remains is how you supply power to the high-side gate driver. The low-side driver gets its power from the low-side power supply \( V_{g0} \). But what provides power where the “???” attaches to VddHS? We need typically 12-15 volts above node “A”, which is switching up and down between the positive and negative terminals of the half-bridge.

If the power stage transistors QAH and QAL are expensive — meaning you’re already spending lots of money on power electronics, so there’s not as much cost sensitivity to the gate drive components — then it might be possible to use a floating DC-DC converter to provide roughly the same voltage \( V_{g0} \) and connect it across the VddHS and VssHS nodes, to power the high-side driver. That costs extra money, though.

Low-cost half-bridge stages typically take a different approach, using bootstrap capacitors and diodes, as shown below:

Typical bootstrap gate drive circuitry

How does this work? Whenever the low-side transistor QAL is on, output node A is very close to \( V_- \), and the bootstrap diode \( D_{boot} \) conducts, charging up \( C_H \) from \( V_{g0} \). When QAL turns off and QAH turns on, the diode \( D_{boot} \) stops conducting, and the high-side gate drive power comes from the energy stored in \( C_H \).

This approach is generally inexpensive, costing just a fast bootstrap diode capable of withstanding the reverse voltage \( V_{DC} \) (and often a series resistor, to limit current spikes through the bootstrap diode). But there’s a performance hit with bootstrap diodes that require some minimum low-side transistor duty cycle to keep the bootstrap capacitor charged — this minimum duty cycle reduces the range of the average output voltage from the half-bridge. And there’s a design cost to ensure that the bootstrap circuit works correctly, namely managing the supply voltages of the high-side output stage, which have even more reasons to vary from the nominal design voltage than the low-side output stage:

  • The bootstrap power supply isn’t the same voltage as the low-side power supply. Just because transistor QAL turns on doesn’t mean that output node A is pulled to the same voltage as the low-side DC link voltage \( V_- \): there’s going to be voltage between the drain and source of QAL, and voltage across any sense resistor. As a result, you might end up with a bootstrap supply that is a volt or two higher or lower than the low-side \( V_{g0} \), depending on the direction of load current \( I_L, \) so if the low-side power supply \( V_{g0} \) is 12 V then the voltage across \( C_H \) might vary anywhere from 10.5 V to 15 V.

  • The bootstrap power supply isn’t recharged long enough. There is a minimum duty cycle on the low-side MOSFET QAL required to ensure the high-side capacitor \( C_H \) is sufficiently recharged. (Some gate drive chips, like the TI DRV8334, contain their own internal charge pump circuitry so that the high-side MOSFET can be turned on indefinitely. You just give it a capacitor and it does the rest.)

  • The bootstrap power supply droops too much during the switching cycle. After QAH is turned on, the capacitor \( C_H \) will droop, as the high-side supply quiescent current discharges this capacitor.

For all these reasons, high-side bootstrap supplies are hard to control precisely, and might vary 4-6 volts between extremes. On the low end you want to make sure the minimum voltage is enough to guarantee the MOSFET in question meets its on-resistance spec for Rdson. On the high end you want to make sure a high maximum voltage doesn’t slow down turn-off too much (the higher the drive voltage, the longer it takes for the MOSFET gate to discharge) and that it doesn’t exceed the MOSFET’s gate voltage rating.

Do your homework! Take component tolerances into account, and measure your system under worst-case conditions to verify that the high-side supply voltage is within its expected range.

Negative voltage transients

On top of these voltage selection issues, there’s a sensitivity on one of the pins to inductive spikes when the high-side MOSFET switches off, where you can get negative voltage transients. Make sure you’ve chosen a gate drive IC with a decent amount of margin, so it can withstand negative voltage spikes. Many gate drive ICs have at least 5V of design margin for negative spikes; for example, here’s the MIC4104’s absolute maximum ratings:

It’s the HS pin that’s going to be hit by this issue, and the MIC4104 says it can withstand -1V indefinitely, and repeated transients of -5V.

Pins that can withstand negative voltage spikes have to be designed specially for this purpose. Otherwise you end up with a more typical silicon limit of a diode drop below the negative supply, like the MIC4604, which can withstand only -0.3V indefinitely, and repeated transients of -0.7V:

Or the Vishay SiP41108, from the mid-2000s, which had an absolute maximum rating for the LX pin of -0.3V:

The telltale sign that this IC is sensitive to negative voltage spikes is the Schottky diode shown innocuously in parallel with the low-side MOSFET… brute force is certainly one way to “solve” the problem, but watch out for where you place that diode in the layout, because it’s going to have its own series inductance.

There are more reasonable workarounds; you can put a resistor and diode clamp to protect the gate drive, as shown in the MIC4604 datasheet:

But adding a resistor and diode clamp reduces the performance of the gate drive, and makes it harder to design to ensure switching time requirements, and adds a slight cost that you could be using to buy a gate drive IC designed to withstand negative voltage spikes. So I would treat the diode clamp as a last resort, to be avoided — instead, buy a good gate drive IC that doesn’t need it.

Oh, and there’s one more gotcha at startup.

Startup behavior with bootstrap gate drives

Remember, you’re going to put some bypass capacitors for the gate drive supplies, shown as \( C_L \) and \( C_H \) in the “Typical bootstrap gate drive circuitry” diagram. Charging up the low-side bypass capacitor \( C_L \) isn’t a big deal: it happens at power-up, and if there’s any undervoltage transient that holds the gate drive IC in reset then it’s no problem, because your whole system is starting up. But charging up the high-side bootstrap capacitor \( C_H \) is a manual task that needs to happen both after reset, and anytime you’ve left both transistors off for long enough for this capacitor to discharge. Your system has to turn the low-side transistor QAL on to charge up \( C_H \) first. I’ve worked on systems where, if you decide all of a sudden to charge the high-side capacitors, they take a big gulp of charge, which can cause an undervoltage on the gate drive power supply for \( V_{g0} \), and this produces a fault, which you have to somehow distinguish from a real undervoltage fault.

As a result, there’s usually some kind of soft-start behavior you need to implement in firmware, where you turn QAL on with a very small duty cycle, and gradually increase it, so that the current from the \( V_{g0} \) supply to charge the capacitor \( C_H \) isn’t very large. This might take only a millisecond or so, and in a three-phase bridge, maybe you have to do it staggered in sequence for each of the three phases, rather than simultaneously, so that the transient charging currents from each phase (GULP GULP GULP!) don’t add up enough to cause an undervoltage.

Layout Notes

I want to talk very, very briefly about layout. This is not my forte, so do your own research, but there is one general principle common to most switch-mode power supply circuits:

  • Minimize loop area of any high-speed circuit. Know where the currents are flowing when you are trying to switch these transistors on or off fast, and you’ve got capacitors that have to be charged or discharged. The larger the loop area, the higher the parasitic inductance, the more likely you will have radiated emissions, and the more susceptible your circuit is to noise. (Again, that source inductance path is the most critical!)

If you look at example boards for power converters, the good ones will use very tight layouts. Look at the gate drive IC datasheets and application notes for suggestions.

Feature Cornucopia / Feature Creep

Some of these gate drive ICs have all sorts of features built in — after all, digital control is cheap these days, what with transistors getting smaller and faster. Make sure you review the datasheet carefully. IC designers put in a great deal of thought and effort before pulling the trigger on a silicon design, but there can be cases where the designer’s assumptions are not consistent with your requirements. So beware of features. Here are a few of the good, the bad, and the ugly:

  • Undervoltage/overvoltage lockout — as discussed earlier, it’s a good idea to shut down the gate drive if the supply voltage is out of range. Just make sure the tolerance on the supply and the tolerance in the detection range don’t add up enough to cause nuisance trips.

  • Voltage isolation — it’s a good idea, especially when running on AC mains power or the kind of high-voltage battery found in electric vehicles (400V - 800V), to separate low-level control circuitry from the power stage with galvanic isolation. This isolates microcontrollers from the risk of short circuits and interference from high-power switching spikes, and makes it possible to measure control signals safely during development and troubleshooting.

  • Integrated op-amps / comparator / reference for current sensing and overcurrent detection — it’s always nice to need fewer ICs to do the things you need. Op-amps for amplifying the signal from a current shunt, and comparators and references for automatic overcurrent detection, are found in many gate drive ICs. (TI’s DRV8334 even has a built-in programmable-gain amplifier (PGA) with ± 0.5% maximum gain error, so you don’t have to add any external gain-setting resistors.) Just watch out for a few gotchas:

    • Op-amp gain-bandwidth product (GBW) — current sense resistors are intentionally low-resistance to avoid overheating and wasting power, so you’ll likely need to add an amplifier with some gain. For example, if you’re trying to measure within the ±50 A range, with a 3.3 V mixed-signal controller, to make best use of the ADCs, the signal gain should be below but near 1.65 V / 50 A = 0.033 V/A = 33 mΩ. But if I want to keep the power dissipation of the sense resistor \( R_S \) below, say, 2.5 W, then that means \( I^2R_S = (50 {\rm A})^2 R_S < 2.5 {\rm W} \), and if you do the math, that means \( R_S < \) 1.0 mΩ. That implies current sense gains of 25 - 30 to take a signal across a 1 mΩ resistor and bring it up to a 25 - 30 mV/A range to get close to the full ADC range. But the higher gain you have, the less bandwidth there is. I worked on one design where we used the TI DRV8334. Its op-amps have a minimum unity-gain bandwidth of 10 MHz, which sounds good, but if you need a gain of 20 then that means a bandwidth of 10 MHz / 20 = 500 kHz, which is not very high, and larger gains have even lower bandwidth: a gain of 30 means a bandwidth of 10 MHz / 30 = 333 kHz. I’d like to see at least 1 MHz current sense bandwidth for any half-bridge using a resistor in the negative phase leg, since it affects minimum practical duty cycle for the half-bridge: you have a limited time to measure the sense resistor current.

    • Tolerance in voltage reference — just make sure any overcurrent or overvoltage detection turns on before it needs to, and after it shouldn’t. The wider the tolerance on a voltage reference, the more difficult this is.

  • Dead-time insertion — it’s useful to ensure, by design, that the upper and lower transistors will never both be on simultaneously, otherwise shoot-through will occur. Some gate drive ICs have an automatic feature for driving complementary pairs of transistors, that will inhibit turning on both output drivers at the same time, and for a specified period of time (dead time) after one transistor has turned off. This is generally a good idea, except:

    • the responsibility for managing this timing generally belongs with the microcontroller that generates the PWM, where this timing can be controlled accurately as a number of digital clock cycles. Even the built-in RC oscillators on microcontrollers these days are specified in the 1-2% accuracy range, due to the need to drive UARTs; if you’re using a crystal oscillator, that accuracy gets down to the 100 ppm range. A standalone gate drive IC isn’t likely to have its own accurate timebase, so there will be tolerance in any time interval it generates. For example, the DRV8334 has anywhere from 20 - 40% dead time tolerance, depending on the setting. The LM5106, which has a dead time programmable with an external resistor, doesn’t even list a worst-case tolerance range, just typical values of 510 ns with a 100 KΩ resistor, and 86 ns with a 10 KΩ resistor.

      What’s the minimum or maximum dead time? I dunno; no guarantees — this part isn’t something I would use. So how are we supposed to guarantee that the dead time we need is sufficient, but not excessive, when there’s a lot of tolerance? Like I said, dead time should be set by the microcontroller, where it can be done precisely, not the gate drive.

    • some topologies need to allow cross-conduction. Admittedly, this is rare, but you can find Z-source inverters out there, with inductance between the supply and the power stage, where successful operation requires short intervals of overlap between upper and lower transistor conduction.

  • Digital configuration — once you put digital logic on a gate drive IC, now you can add control registers to adjust almost anything, and all you need is a few digital lines for UART or SPI, so that your system microcontroller can set up the gate drive IC the way it wants. Want to set the source and sink currents by setting registers? Sure, go ahead! In theory this is a good idea, and removes the need for external components, but my only worry is whenever there is communication between separate ICs, even if in close proximity on the same board, there is always a chance for bit errors to occur. Look closely at the datasheet, and see if there are features for ensuring reliable communication, like a CRC or at the very least a parity check. Otherwise you could have something operating incorrectly, and you’d never know it. At the very least, read back all your control registers.

Testing and Reliability

The last topic I want to talk about today is testing and reliability. How do you make a power stage work reliably?

And it really does have to be reliable — the last thing you want is POP! to let the magic smoke out and deal with damage in production boards. Failures during development are not as costly for a company, but they can delay time to market, and you really don’t want to have a finger-pointing argument between software/controls teams who are working on a digital controller, and the power electronics engineers who are responsible for the gate drive design. Remember, the firmware in a digitally-controlled power converter does usually have the ability to cause power device failure.

I’m going to repeat this point for emphasis: Firmware in a digitally-controlled power converter usually has the ability to cause power device failure. If I chose to, I could write microcontroller code to turn on transistors and cause them to overheat. There is almost no way to completely protect a power device from bad firmware, without adding lots of cost or reducing the performance envelope.

In my mind there are really four things you need:

  • Design transistor drive so that the switches are normally open — in most circuits, switches should be off as a failsafe condition.
  • Design with failure detection/prevention in mind — how do you protect against failures and prevent them from spreading?
  • Design with component tolerances in mind — make sure that you’ve used a conservative enough design margin
  • Testing — put your system through stress-testing during its development!

Design for normally open switches

Always make sure that the transistors default to an off-state. With MOSFETs and IGBTs, this means that there’s some circuit to pull charge out of the gate; at the very least a high-value pull-down resistor, perhaps 100 KΩ or some other value that doesn’t degrade the on-voltage capability significantly.

Some gate drive ICs have an internal pull-down circuit, but make sure it’s specified so that you’re confident it will pull charge out of the gate of the power device, even if the gate drive IC power is removed.

Other gate drive circuits have pull-down resistors in the right places to discharge the gate, like this one I showed earlier:

These resistors at or near the gate will help in the event there’s a failure of the gate drive IC or its power supply. You also need to make sure that the controller producing PWM signals has a way of ensuring inactive inputs to the gate drive IC if something goes wrong upstream. If you’re using a microcontroller with PWM outputs, in many cases those outputs will revert to a high impedance state during reset — double-check that your gate drive IC has internal bias current or pulldown resistors so that when the PWM signals are high-impedance, the gate drive IC treats that as an OFF state. For example, in the LF21814N block diagram I showed earlier, there are internal pulldowns connected to HIN and LIN:

Of the gate drive ICs I have cited in this article, most seem to have this feature:

  • 1ED3431M: Internal “logic input pull down resistor”, 33 KΩ – 47 KΩ
  • DRV8334: “Input pulldown resistance” to INHx and INLx pins: 50 KΩ – 150 KΩ
  • LF21814N: unfortunately, the resistance is unspecified, and there are specs on maximum input bias current but not minimum bias current. I wouldn’t use this part because of the lack of specifications.
  • LM5106: “Input Pulldown Resistance”, 100 KΩ – 500 KΩ
  • MCP1401: No pulldown; inputs are high-impedance CMOS inputs.
  • MIC4103: “Input Pull-Down Resistance”, 100 KΩ – 500 KΩ
  • MIC4604: “Input Pull-Down Resistance”, 100 KΩ – 500 KΩ
  • SG1627: unclear from datasheet, but we should probably forgive 1970s IC designers.
  • SiP41108: No pulldown; inputs are high-impedance CMOS inputs.

Be sure to use the watchdog reset feature in microcontrollers, so that if the firmware locks up, it will reset the microcontroller, and the gate drive circuitry will turn off the power devices.

Fault detection

Many faults are foreseeable, and today’s gate drive ICs often have undervoltage or overcurrent or even “desat” detection built-in. Let’s go over these failure conditions and failure mechanisms one by one.

First, the underlying failure mechanism, which in a power transistor is usually overheating — if the junction temperature is rated at 175°C, and you keep the temperature of the entire die below that rating, almost anything can happen to the transistor without causing damage. There are a few exceptions:

The avalanche current is composed of high energy charge carriers moving through the depletion region. As they pass through, they can collide with the Si structure. There is a chance that a high energy carrier (sometimes called a hot carrier) is produced that collides with the gate oxide causing damage. It is not completely destroyed but it does cause it to wear out, which is observed as parameter variation.

  • mechanical damage to the die or bond wire attachments caused by extreme thermal gradients or thermal cycling

But chances are, if you have damaged a power transistor, it’s because it got too hot somewhere inside. Eventually the transistor will fail open or fail shorted, and this may cause further damage in other circuit components.

There are several failure conditions that can be caught at an early stage, in hardware, to prevent fault propagation:

  • Overcurrent — current flowing through a transistor will dissipate power and cause it to heat up. Hardware overcurrent detection can sense excessive current and turn off the gate drive. An “overcurrent” condition means different things to different people, so it helps to subclassify overcurrents:

    • Slow overcurrents — Let’s suppose your half-bridge has good thermal management to dissipate I²R losses, and could handle 10 A continuously, or 12 A for ten minutes, or 30 A for ten seconds without overheating. If there’s some kind of software or measurement error in the control electronics and it sees 12 A for more than ten minutes, or 14 A for ten minutes, then the device may overheat. Overcurrent detection in hardware isn’t going to help you with this kind of situation: it’s too difficult to make accurate measurements of current over time that won’t cause false trips during normal operation. This kind of scenario needs to be handled in firmware, in combination with temperature sensors where possible.

    • Fast overcurrents — Let’s suppose you have a digital current regulator that controls current to a nominal value of more than 50 A. And suppose this controller may overshoot, with a worst-case design limit of 10% (55 A nominal during the overshoot). And suppose the current sensing has a worst-case tolerance of ±2%. And maybe there’s a worst-case superimposed ripple of 2.4 A due to the interaction of pulse-width modulation with the load inductance. (We talked about this in Part 1.) And maybe there’s 1.5 A of noise in the system. This is the worst-case “normal” operation, and overcurrent detection should be set so that it trips with no less than 55 A × 1.02 + 2.4 A + 1.5 = 60.0 A. If the current regulator performs worse than normal for some reason, and the current rises above this level, it is okay to detect as an overcurrent.

    • Shoot-through / severe short circuits — Suppose the upper transistor of the half bridge fails shorted, and the lower transistor turns on. This can cause hundreds of amperes to flow, and it’s this condition that we’d like to detect and shut off the gate drive before the lower transistor also fails. Power transistors can typically withstand high currents for 5 – 10 μs without damage, so as long as we can detect a large amount of current and shut off before that time, we can prevent further fault propagation.

    For these reasons, I usually recommend an overcurrent detection circuit that has a threshold that is just above the worst-case “normal” operation, including worst-case tolerance, control overshoot, current ripple, and noise. This is a worst-case threshold, so the nominal overcurrent threshold has to be designed to a larger value than that to accommodate component tolerances. Hardware overcurrent detection isn’t there to catch slow thermal events or control failures; we really just want to catch the gross overcurrent conditions.

  • Undervoltage — The gate drive supply voltage \( V_{g0} \) needs to be high enough to turn on the transistors reliably. If my 12V supply has some problem and sags down to 9V, I can no longer guarantee the datasheet spec for Rdson at 10V, and the conduction loss in the transistor might increase. Many gate drive ICs will have undervoltage lockout to avoid this condition.

  • Overvoltage — If the DC link voltage on the half-bridge gets too high, it can exceed the breakdown voltage of the transistors or capacitors. A good overvoltage detection circuit will catch this and shut down the gate drive before further damage is caused. As in the case of overcurrent, any thresholds should be set so that they never cause false trips during normal operation, but will detect a severe overvoltage.

  • Desaturation (or “desat”) — this is the condition where the drain-source voltage across the power transistor starts to rise, either because it’s carrying too much current or it doesn’t have enough gate drive voltage, and it no longer looks like an on/off switch but rather a linear, dissipative device. Some gate drive ICs have this built-in, or support an input through a diode to turn off the gate drive.

In all of these scenarios, you want the transistor to turn off quickly enough to avoid further damage. And in general, any fault detected in hardware should stay latched until a high-level system controller can look at it, and either try operating again or report the fault condition.


I’ve been trained to design around worst-case component tolerance. Sometimes people look at me funny when I go through the effort of tolerance analysis, and I tell them, well, if this resistor is 1% high and this resistor is 1% low and if this voltage regulator is at its low end, and it’s +125°C and the diode drop is down at its low end, then we could see 9.2 V and that’s not enough to guarantee the transistor will turn on. But when that one-in-a-million board is manufactured that runs into those conditions in just the right way, you have a problem. So make sure you use conservative enough design margin and take into account component tolerances.

I mentioned this in the section on managing supply voltage: for example, the bootstrap supply voltage needs to be sufficient at its worst-case low end, given component tolerances, to guarantee the high-side transistors are turned on with enough voltage to support their specified behavior; conversely, bootstrap supply voltage can’t be excessively high at the other end of the tolerance range.

The same principle also applies to switching time. In this article, I explained all of the switching time calculations with nominal values, to show how to do the calculations. But if you’re designing a gate drive, you need to repeat these calculations for worst-case component tolerance variation: voltage threshold, charge, resistance and capacitance, supply voltage, load current, Rdson, etc. This will give you worst-case switching times, so you can select a dead time that is sufficient in all cases.


You want to make sure your power electronics design is robust? Put it through its paces and don’t be delicate!

  • Run it at its full load rating in the highest expected ambient temperature. If the load rating is not a constant value but depends on ambient temperature, make sure you test it several places across the temperature range. (In other words, if you’ve designed it for 10 A continuous at 85°C ambient, 15 A continuous at 25°C, and 20 A continuous at -40°C ambient, you’d better test at least all three of those operating points.)

  • Check it at the high and low ends of the DC link operating range, as well as the nominal operating voltage.

  • If you have overcurrent detection (and you should), put a short across one of the transistors in the half-bridge, and make sure it shuts down the gate drive properly.

  • Make sure the gate drive supply voltages aren’t too high or too low. This can be tricky to check, especially with the high-side drive, where the node voltages are zooming up and down, and the measuring device can affect the operation of the gate drive circuitry.


Whew! We’ve talked about a whole bunch of topics related to power MOSFET and IGBT gate drives:

  • What happens in the various stages during the turn-on or turn-off transients of a transistor
  • How to estimate the time needed for turn-on or turn-off, using transistor specifications
  • What kinds of resistors/capacitors/diodes (“jewelry”) are typically located between the gate drive IC and the power transistor
  • Delays and transients caused by diode reverse recovery at transistor turn-on
  • Reasons to increase or decrease turn-on and turn-off time
    • shorter times = lower switching losses
    • longer turn-on = lower reverse recovery losses
    • longer turn-on = lower chance of capacitively-coupled spurious turn-on in a half-bridge
    • longer turn-on and turn-off time = lower EMI
  • Management of gate drive power supplies
  • Bootstrap gate drive circuits, including the issue of negative voltage spikes
  • Various features found in gate drive ICs, and why some of them may not be as well-designed as you think
  • Issues involved in reliability and fault detection

I hope I’ve convinced you that designing a power transistor gate drive is a serious effort, not to be underestimated. If you’re new to this area of power electronics, seek help from others who are experienced, and do your homework. Keep those transistors operating safely, and save the smoke for your summer barbecues!

Thanks for reading!



General topics

Gate drive circuit design

Device characteristics

Switching time, power loss, or waveform analysis

Spurious capacitively-coupled turn-on

Diode reverse recovery

MOSFET operation in the linear (sub-threshold) region

Parasitic oscillation

Avalanche and hot-carrier degradation

Single-event effects

Reliability and failure

Why a first-order Thevenin equivalent of a gate drive diode is good enough

To analyze turn-off current vs. voltage when there’s a turn-off diode, we need a way to approximate the diode.

In my recent article on modeling gate drive diodes, I transformed the diode to a Thevenin equivalent for the entire circuit:

I showed three ways of modeling diode voltage:

  1. Zero-order approximation: \( V_D = \) 390 mV as long as current through the diode is positive (gate voltage > 488 mV) and zero current otherwise. For the positive current case, the Thevenin equivalent (bottom circuit above) is therefore \( V_{TH0} = \frac{R_2}{R_1+R_2}V_D = \) 312 mV with \( R_{TH0} = R_3 + (R_1 \parallel R_2) = \) 4.5 Ω total series resistance, so the turn-off current is:

    $$ I = \max\left(\frac{V_g - V_{TH0}}{R_{TH0}}, \frac{V_g}{R_3+R_2}\right) $$

  2. First-order approximation: \( V_D = \) 343 mV, with series resistance \( R_D = \) 94.6 mΩ for each of the two diodes, or \( R_D = \) 47.3 mΩ for them both in parallel, as long as current through the diode is positive (gate voltage > 429 mV), which we got from the Shockley model (see third method). Then the Thevenin equivalent (bottom circuit above) is \( V_{TH1} = \frac{R_2}{R_1+R_D+R_2}V_D = \) 273 mV and \( R_{TH1} = R_3 + ((R_1 + R_D) \parallel R_2) = \) 4.53 Ω total series resistance, so the turn-off current is:

    $$ I = \max\left(\frac{V_g - V_{TH1}}{R_{TH1}}, \frac{V_g}{R_3+R_2}\right) $$

  3. Shockley model with added lead resistance: \( V_D = I_DR_D + \frac{nkT}{q} \ln \left(\frac{I_D}{I_S}+1\right) \)

In that article, we digitized points from a datasheet graph showing typical forward voltage, and fit to the equation above using least-squares, determined \( R_D = \) 86.5 mΩ, \( I_S = \) 3.466 μA, and \( \frac{nkT}{q} \) = 26.4 mV for typical diode behavior, adding a fudge factor of 390 mV / 356 mV to match the worst-case datasheet value.

I would use the first-order approximation for further analysis, because it is piecewise linear, so we can easily analyze the exponential behavior that comes from linear RC circuits.

We could use the Shockley model and solve for turn-on/turn-off time numerically, but that complicates things. In the article on gate drive modeling, I generated the graph above by letting the diode current \( I_D \) be the independent variable, and figuring out everything else from it. Otherwise it’s more difficult to solve for \( I_D \) given circuit voltages. It’s possible to use this independent-\( I_D \) approach with time analysis as well. Here’s an example of how to do so, and I’ll show why it’s not necessary:

Suppose we are trying to figure out the gate voltage discharge vs. time curve from the Miller plateau at the 2.7 V we’ve been assuming throughout this article, and we use the same Cgs = 1700 pF assumption.

With the first-order linear model, it’s easy; from 2.7V down to 429 mV we have an exponential decay toward the Thevenin voltage \( V_{TH1} = \) 273 mV:

$$V_{GS} = V_{TH1} + (2.7 - V_{TH1})e^{-t/R_{TH1}C_{GS}}$$

This takes \( R_{TH1}C_{GS} \ln (2.7 - 0.273)/(0.429 - 0.273) = \) 21 ns, and then after reaching 429 mV, we have an exponential decay toward zero with time constant determined by \( C_{GS} \) and (R3 + R2).


The Shockley model requires us to integrate numerically, and the easiest way to do so is by starting at the diode current we get at a gate voltage of 2.7V, and then ramping down to zero to solve for time.

import numpy as np
import pandas as pd
import scipy.optimize
import matplotlib.pyplot as plt
%matplotlib inline

R1,R2,R3 = 2.5,10,2.5
Rd = 0.0865

def fVd(Id):
    Id1 = Id / 2                       # two parallel diodes sharing current equally
    Rd = 0.0865
    Is = 3.466e-6
    nkTq = 0.0264
    Vd_typ = Id1*Rd + nkTq*np.log(Id1/Is + 1)
    return Vd_typ * 390/356.5          # scale for worst-case 390 mV at 500 mA

def f_Vg_I_from_Id(Id):
    Vd = fVd(Id)
    I = (Id*(R1+R2)+Vd)/R2
    Vg = I*R3 + Vd + Id*R1
    return Vg,I

def g_Id_from_Vg(Vg, Id1, Id2):
    return scipy.optimize.brentq(lambda Id: f_Vg_I_from_Id(Id)[0] - Vg, Id1, Id2)

Id_plateau = g_Id_from_Vg(2.7, 0.2, 0.5)
Id = np.arange(4054)[::-1]/10000
Vg, I = f_Vg_I_from_Id(Id)
df = pd.DataFrame(dict(Id=Id, Ig=-I, Vg=Vg))
Id Ig Vg
0 0.4053 -0.540243 2.700036
1 0.4052 -0.540117 2.699459
2 0.4051 -0.539991 2.698882
3 0.4050 -0.539864 2.698305
4 0.4049 -0.539738 2.697727
... ... ... ...
4049 0.0004 -0.012264 0.149295
4050 0.0003 -0.011324 0.138545
4051 0.0002 -0.010060 0.123744
4052 0.0001 -0.008027 0.099342
4053 0.0000 -0.000000 0.000000

4054 rows × 3 columns

During each step, we can take the average current and the change in gate voltage and figure out how long it took to go through that step with \( I_g \approx C_g \frac{\Delta V_g}{\Delta t} \).

For example, going from \( I_d = \) 0.4053 A to 0.4052 A:

  • average turn-off current \( I_g \) was -0.54018 A
  • change in gate voltage \( \Delta V_g \) was -0.000577 V
  • therefore the time of this step \( \Delta t \approx C_g \frac{\Delta V_g}{I_g} \) = 1700pF × -0.577mV / -0.54018 A = 1.816 ps

We can do the same for the first-order linear method, both numerically and analytically (two exponential decays, the first toward \( V_{TH1} \) and the second toward zero, as described earlier), and see what we get:

Cg = 1700e-12
Vg_plateau = 2.7

def solve_for_time_numerically(Vg, Ig):
    delta_Vg = np.diff(Vg)
    Ig_avg = (Ig[:-1] + Ig[1:]) / 2
    delta_t = Cg * delta_Vg / Ig_avg
    t = np.hstack([0, np.cumsum(delta_t)])
    return t

# Shockley equation
t = solve_for_time_numerically(Vg, -I)

# First-order approximation
Vth1 = 0.273
Rth1 = 4.53
Vg1 = np.arange(Vg_plateau,0,-0.0002)
I1 = np.maximum((Vg1-Vth1)/Rth1, Vg1/(R3+R2))
t1 = solve_for_time_numerically(Vg1, -I1)

# Analytical solution to first-order approximation
def solve_analytically(t, Rd, Vd, Vstart):
    Vth = R2/(R1+R2)*Vd
    Rth = 1/(1/(R1+Rd) + 1/R2) + R3
    Vbreakpoint = Vd * (R3+R2)/R2
    tbreakpoint = Rth*Cg*np.log((Vstart - Vth) / (Vbreakpoint - Vth))
    Vg = Vth + (Vstart - Vth)*np.exp(-t / (Rth*Cg))
    Vg[t > tbreakpoint] = Vbreakpoint * np.exp(-(t[t>tbreakpoint] - tbreakpoint)
                                               / ((R2+R3)*Cg))
    return Vg, Vbreakpoint, tbreakpoint
ta = np.arange(0,100e-9,0.1e-9)

Vg1a, Vbreakpoint1, tbreakpoint1 = solve_analytically(ta, Rd, Vd = 0.343, 
                                                      Vstart = Vg_plateau)
Vg0a, Vbreakpoint0, tbreakpoint0 = solve_analytically(ta, Rd=0, Vd = 0.390, 
                                                      Vstart = Vg_plateau)

# now graph them
def scaling_formatter(scale, fmt='%f'):
    def format_func(value, tick_number):
        return fmt%(scale*value)
    return plt.FuncFormatter(format_func)

import PIL
import urllib

url = 'https://live.staticflickr.com/65535/53576720052_2522c5c7f1_o.png'
circuit_png = np.array(PIL.Image.open(urllib.request.urlopen(url)))

fig,ax = plt.subplots(figsize=(10,8))
axin1 = ax.inset_axes([0.35, 0.39, 0.6, 0.45], xticks=[], yticks=[])
axin1.imshow(circuit_png, cmap='gray')
ax.plot(t,Vg,label='Shockley model, numerical',linewidth=1.0)
hl = ax.plot(t1,Vg1,label='First-order approximation, numerical',linewidth=1.0)
ax.plot(tbreakpoint1, Vbreakpoint1, '.', color=hl[0].get_color())
ax.plot(ta,Vg1a,label='First-order approximation, analytic',
ax.plot(ta,Vg0a,label='Zero-order approximation, analytic', linewidth=1.0)
tmax = 60e-9
ax.set_xticks(np.arange(0,tmax+1e-12,5e-9), minor=True)
ax.xaxis.set_major_formatter(scaling_formatter(1e9, fmt='%.0f'))
ax.grid(which='minor', linewidth=0.25)
ax.set_xlabel('Time, ns')
ax.set_ylabel('Voltage, V')
ax.set_title('Gate voltage turn-off with diode circuit (2x PMEG2005CT)\n'
            +('R1 = %.1f\u03A9, R2 = %.1f\u03A9, R3 = Rdson(Q2n) = %.1f\u03A9,'
              +' Rd = %.3f\u03A9') 
             % (R1,R2,R3,Rd));

There — the first-order approximation is very close to the Shockley model, down to about 0.9V on the gate, which is far below any of the interesting behavior we care about.

So it’s really not worth it to use a full diode model if we’re just interested in determining how long it takes the transistor to get below its turn-on threshold. We can even get away with the zero-order model and treat the diode like a fixed voltage source.

Even the parameter uncertainty of gate capacitance and diode voltage is greater than the error of a zero-order approximation; we’re lucky if we can get those within a few percent.

© 2024 Jason M. Sachs, all rights reserved.

[ - ]
Comment by DennisChiJuly 4, 2024

You have repeated a sentence in the description of t3 below the switching waveforms. The following should be removed: "During this interval, load current shifts from the other transistor in the half-bridge to this transistor. But the voltage across the transistor is still the full DC link voltage Vdc𝑉𝑑𝑐, and at the end of this interval, power dissipation in the transistor reaches its maximum I1Vdc𝐼1𝑉𝑑𝑐."

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