Hello, I'm trying to change parallel bus to EMIF mode, but I don't know how to do it from source code. It goes to HPI mode when because of...

Hello, I'm trying to change parallel bus to EMIF mode, but I don't know how to do it from source code. It goes to HPI mode when because of BOOT3 (IO.0) is 0 during power up (bootloader uses serial EEPROM). I'm trying to write EBSR register (0x6c00) but it doesn't work. Can it be done dynamically (datasheet doesn't recommend that) and how? thanks, Janne

Scottie- > I have a USB device hooked off my 5510s EMIF, and can use it quite > happily using asynchronous mode on both DSP and USB...

Scottie- > I have a USB device hooked off my 5510s EMIF, and can use it quite > happily using asynchronous mode on both DSP and USB device. Small problem at this point... USB should be connected to either a) McBSP directly or b) McBSP via small glue logic. For example, use a small CPLD or one of Lattice's cool new small FPGAs with built-in config RAM, connect 8-bit parallel to USB device

Hi All, I have a USB device hooked off my 5510s EMIF, and can use it quite happily using asynchronous mode on both DSP and USB...

Hi All, I have a USB device hooked off my 5510s EMIF, and can use it quite happily using asynchronous mode on both DSP and USB device. However, when the USB device runs in asynchronous mode it is not capable of reaching the high USB2 bandwidth figures I require. To achieve this, I need to run the DSP device in synchronous mode. Initially I thought, no problem, I'll just run the 5510...

Hello All, I have a very hard time trying to make the EMIF in TMS320VC5509APGE-4A working stable at 192MHz. The test conditions:...

Hello All, I have a very hard time trying to make the EMIF in TMS320VC5509APGE-4A working stable at 192MHz. The test conditions: Hardware: DSP: TMS320VC5509APGE-4A Vdd=3.3V, Vcore=1.6V We have a supervisor which monitors Vdd, Vcore and manual reset button Crystal: 12 MHz, CPU works at 192 MHz LEDs on: GPIO0 - Green, GPIO1 - Red ARDY pin is pulled up using 2...

Hi all, I have a 5510 connected to an external device over the EMIF as asynchronous memory, and I want to DMA from internal RAM to this...

Hi all, I have a 5510 connected to an external device over the EMIF as asynchronous memory, and I want to DMA from internal RAM to this device. I also want to run my CPU at full speed (200MHz), which gives a CPU cycle of 5ns. However, the timing constraints when writing to my external device require me to configure a minimum hold period of 70ns before I can re-assert the write s...

Hi all, I have a problem with write to TMS320C5509 emif. I write to a typical addresse in ce spaces: (IO_PORT = 0x400000)...

Hi all, I have a problem with write to TMS320C5509 emif. I write to a typical addresse in ce spaces: (IO_PORT = 0x400000) like this: *(volatile unsigned int*) IO_PORT = 0xAAAA but CE signals and data signals are not seen. my CE signals does not chan

Or a larger SDRAM? The largest one readily available that fits standard JEDEC site is 8M x 32, or 256 Mbit. -Jeff ...

Or a larger SDRAM? The largest one readily available that fits standard JEDEC site is 8M x 32, or 256 Mbit. -Jeff -------- Original Message -------- Subject: [c55x] 5502 EMIF / SDRAM Interface Date: Tue, 25 Jan 2005 10:29:19 -0600 From: Ryan Piwowarsk

Hi, I am working on OMAP1510 board. I need to interface external SDRAM with DSP(C55x), without using ARM. I tried using EMIF...

Hi, I am working on OMAP1510 board. I need to interface external SDRAM with DSP(C55x), without using ARM. I tried using EMIF configuration manager in DSP BIOS cdb file but could not succeed. Shall I need to do anything else after inserting EMIF configuration in cdb file?

Hi, I am trying to configure EMIF to write/read to/from external memory. Below I am including linker cmd file and source code. I am unable to...

Hi, I am trying to configure EMIF to write/read to/from external memory. Below I am including linker cmd file and source code. I am unable to notice any changes using oscilloscope on address pins A0-A2 and data pins d0-d7. Also CE1 always remains high. I would appreciate if someone might be able provide me some comments. MEMORY { MMR : o = 0x000000 l = 0x0000c0 DARAM0 : o = 0x0...

Hello Jeff, It is my board. The peripheral I mentioned is an image sensor which is a standard asynchronous memory. It is interesting that...

Hello Jeff, It is my board. The peripheral I mentioned is an image sensor which is a standard asynchronous memory. It is interesting that even without this sensor connected, the problem still exists. I think that the answer Andrej Novak gave me relates closely with my problem as I have observed strong correlation between enabling/disabling of the signal from "clockout " pin and th...

Hi, I am trying to get familiar with the DSK5509a for a project. My first task was to write and read something(an integer, a string..) from...

Hi, I am trying to get familiar with the DSK5509a for a project. My first task was to write and read something(an integer, a string..) from the RAM memory, which i successfully did. Next, I have to do the same, but on the flash memory. Lately i have read a lot of articles, data manuals, and posts, about flashburn, EMIF, bootloaders, DMA ...etc and to be honest my head is mixed up right now. I ...

Andrej- Your answer is great -- that must have been some debug battle to figure it out. Just lab work, not in the docs, no obvious...

Andrej- Your answer is great -- that must have been some debug battle to figure it out. Just lab work, not in the docs, no obvious clues... It's gems like this that renew my faith in tech group collaboration. I can give 20 answers on the group, then to see one pop up like this is the reward. Thanks. -Jeff Andrej Novak wrote: > Hi Mitko, > > We had also hard time trying to make

Hi Michael, Thank you for this information. I think that there is a problem in the PLL design of C5509A. It is good that I manage to get...

Hi Michael, Thank you for this information. I think that there is a problem in the PLL design of C5509A. It is good that I manage to get 186MHz stable operation as I described. Regards Mitko ----- Original Message ----- From: "Michael Schuster" To: ; Sent: Monday, June 26, 2006 5:05 PM Subject: Re: [c55x] Re: TMS320VC5509

Hi I have a custom 5502 board. I have been able to write code to it's SDRAM and execute form there. My problems (unexpectedly) are coming from...

Hi I have a custom 5502 board. I have been able to write code to it's SDRAM and execute form there. My problems (unexpectedly) are coming from flash. i can access it's flash when i burn my code in it and using flashburn i also compared the flash contents of my board versus the EVM5502 board and i found that they were the same. My GPIOs are always(before reset adn after reset i have hard...

Hello all I am trying to run two channels of G.729 vocoder on the c5502 processor. The processor is running at 300 MHz and the external SDRAM (...

Hello all I am trying to run two channels of G.729 vocoder on the c5502 processor. The processor is running at 300 MHz and the external SDRAM ( synchronous interface with the EMIF ), is running at 100 MHz. The complete code (.text) section of G.729 is placed in the external memory. All other sections like the .stack, .const, .cinit, .data are placed inside the inernal memory. I have ena...

Nils- > thanks for the answer. So I guess the peripherial bus and its timing is the reason. > Do you know of any manuals for the 5509 that...

Nils- > thanks for the answer. So I guess the peripherial bus and its timing is the reason. > Do you know of any manuals for the 5509 that state the number of extra cycles the > bus tkes? > Not off hand. My guess would be you could ask the TI hotline for a document. They tend to provide such "hands on measurement" docs, like EMIF throughput, if you can demonstrate you need it and the in

Dear list, I am using custom TMS320VC5501 board. It's using EMIF boot. My application code runs fine either emulator mode or boot mode by...

Dear list, I am using custom TMS320VC5501 board. It's using EMIF boot. My application code runs fine either emulator mode or boot mode by complier and linker under CCS2.21. But when I complier and link it under CCS3.3. It's runing by emulator mode. Under the boot mode, it boots but couldn't run interrupter. The hardware is same and the problem is repeatable. By monitors the GPIO4, ...

Hi , I am working with TMS320C5509A emif and facing a similar problem. When I write address for CE spaces no Chip select is generated. By...

Hi , I am working with TMS320C5509A emif and facing a similar problem. When I write address for CE spaces no Chip select is generated. By default CE signal for CE space CE1 is generated for any address. I am writing address as shown below. *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config Also if I write statement where should i be able to see the data in Memo...

Hi,everyone the TI documents illustrate that two DMA controller can't access the same port simultaneously,and the port defined as DARAM SARAM EMIF...

Hi,everyone the TI documents illustrate that two DMA controller can't access the same port simultaneously,and the port defined as DARAM SARAM EMIF peripheral. so if I implement a program in DARAM spaces use two DMA ????one for read ,anther for write,then their can't work simultaneously in one clock cycle. Could anyone who know about this tell me if my understanding is right? Could CPU and DMA ...

Hello all, I'm looking to interface SDRAM to the 5502. I've been designing embedded systems for 25 years, but unfortunately (or perhaps,...

Hello all, I'm looking to interface SDRAM to the 5502. I've been designing embedded systems for 25 years, but unfortunately (or perhaps, fortunately :)) have never used any type of DRAM. My question is this: Is it possible to manually "bank" SDRAM devices like you can with SRAMs? The 5502 EMIF spec (spru621f) states that 256-Mbit is the largest device that can be used. Can I use, say, ...