Hi, I am working on OMAP1510 board. I need to interface external SDRAM with DSP(C55x), without using ARM. I tried using EMIF...

Hi, I am working on OMAP1510 board. I need to interface external SDRAM with DSP(C55x), without using ARM. I tried using EMIF configuration manager in DSP BIOS cdb file but could not succeed. Shall I need to do anything else after inserting EMIF configuration in cdb file?

Hello All, I have a very hard time trying to make the EMIF in TMS320VC5509APGE-4A working stable at 192MHz. The test conditions:...

Hello All, I have a very hard time trying to make the EMIF in TMS320VC5509APGE-4A working stable at 192MHz. The test conditions: Hardware: DSP: TMS320VC5509APGE-4A Vdd=3.3V, Vcore=1.6V We have a supervisor which monitors Vdd, Vcore and manual reset button Crystal: 12 MHz, CPU works at 192 MHz LEDs on: GPIO0 - Green, GPIO1 - Red ARDY pin is pulled up using 2...

Hi All, I am working on TMS320C55 (OMAP5910). I need to change some registers for EMIF. I do know 16-bit addresses for my registers but I...

Hi All, I am working on TMS320C55 (OMAP5910). I need to change some registers for EMIF. I do know 16-bit addresses for my registers but I cannot write them using CCS. I need to know 32-bit address of that registers so I could write new values in that registers. I do not know 32-bit addresses for my registers but I cannot find any useful documentation that describes necessary addresses. Does...

John- > We've been developing code on a custom PCB for the 5502 chip. We > realized we needed a port expander, so we made a revision to...

John- > We've been developing code on a custom PCB for the 5502 chip. We > realized we needed a port expander, so we made a revision to our > custom board. However, now we are not able to configure the PLL to get > a CPU clock speed above 132 MHz AND have functional SDRAM interface or > peripherals. The emulation freezes when the EMIF is utilized if > PLL_DIV3 is not set to 0x8003, regardl

Hi, We've been developing code on a custom PCB for the 5502 chip. We realized we needed a port expander, so we made a revision to our custom...

Hi, We've been developing code on a custom PCB for the 5502 chip. We realized we needed a port expander, so we made a revision to our custom board. However, now we are not able to configure the PLL to get a CPU clock speed above 132 MHz AND have functional SDRAM interface or peripherals. The emulation freezes when the EMIF is utilized if PLL_DIV3 is not set to 0x8003, regardless of clock ...

Hi all, I have a 5510 connected to an external device over the EMIF as asynchronous memory, and I want to DMA from internal RAM to this...

Hi all, I have a 5510 connected to an external device over the EMIF as asynchronous memory, and I want to DMA from internal RAM to this device. I also want to run my CPU at full speed (200MHz), which gives a CPU cycle of 5ns. However, the timing constraints when writing to my external device require me to configure a minimum hold period of 70ns before I can re-assert the write s...

Scottie- > I have a USB device hooked off my 5510s EMIF, and can use it quite > happily using asynchronous mode on both DSP and USB...

Scottie- > I have a USB device hooked off my 5510s EMIF, and can use it quite > happily using asynchronous mode on both DSP and USB device. Small problem at this point... USB should be connected to either a) McBSP directly or b) McBSP via small glue logic. For example, use a small CPLD or one of Lattice's cool new small FPGAs with built-in config RAM, connect 8-bit parallel to USB device

Hello, i have spent several hours trying to get my Flash Memory (AT49LV1024, 1Mbit) running on EMIF. My Configuration...

Hello, i have spent several hours trying to get my Flash Memory (AT49LV1024, 1Mbit) running on EMIF. My Configuration is: EMIF_FSET(EGCR,MEMFREQ,4); //MEMFREQ 1/16 CPU EMIF_FSET(EGCR,MEMCEN,1); //MEMClock on CLKMEM EMIF_FSET(EGCR,NOHOLD,0); //MEMClock on CLKMEM EMIF_FSET(CE21,MTYPE,1); //16 bit async EMIF_FSET(CE21,RDSETUP,1); //RD Setup Clock Time EMIF_FSET(CE21,RDSTROBE,17); //RD...

Hi All, I have a USB device hooked off my 5510s EMIF, and can use it quite happily using asynchronous mode on both DSP and USB...

Hi All, I have a USB device hooked off my 5510s EMIF, and can use it quite happily using asynchronous mode on both DSP and USB device. However, when the USB device runs in asynchronous mode it is not capable of reaching the high USB2 bandwidth figures I require. To achieve this, I need to run the DSP device in synchronous mode. Initially I thought, no problem, I'll just run the 5510...

Hi all, I need to access the led's on the dsk 5510 . Do i just need to write in the cpld reg. or i have to program the emif . Please...

Hi all, I need to access the led's on the dsk 5510 . Do i just need to write in the cpld reg. or i have to program the emif . Please reply asap. Thanks Steve.

I am trying to access DRAM interfaced with EMIF in C5510 using DMA with CSL. I have modified the example dma1 that do the same for...

I am trying to access DRAM interfaced with EMIF in C5510 using DMA with CSL. I have modified the example dma1 that do the same for internal SRAM. My code is attached but it does not work. Can anybody tell me what is wrong. Regards Farooq

has anyone used this? according to TMS320VC5501/5502 DSP Instruction Cache Reference Guide (Rev. C) (spru630c.pdf), the configuration,...

has anyone used this? according to TMS320VC5501/5502 DSP Instruction Cache Reference Guide (Rev. C) (spru630c.pdf), the configuration, flushing, and enabling is pretty straighforward. however, i assummed that the i-cache contents are viewable in i/o space via ccs. i do not see the fetched instructions via the emif cached anywhere. does anyon

Nils- > thanks for the answer. So I guess the peripherial bus and its timing is the reason. > Do you know of any manuals for the 5509 that...

Nils- > thanks for the answer. So I guess the peripherial bus and its timing is the reason. > Do you know of any manuals for the 5509 that state the number of extra cycles the > bus tkes? > Not off hand. My guess would be you could ask the TI hotline for a document. They tend to provide such "hands on measurement" docs, like EMIF throughput, if you can demonstrate you need it and the in

Hello all, I'm looking to interface SDRAM to the 5502. I've been designing embedded systems for 25 years, but unfortunately (or perhaps,...

Hello all, I'm looking to interface SDRAM to the 5502. I've been designing embedded systems for 25 years, but unfortunately (or perhaps, fortunately :)) have never used any type of DRAM. My question is this: Is it possible to manually "bank" SDRAM devices like you can with SRAMs? The 5502 EMIF spec (spru621f) states that 256-Mbit is the largest device that can be used. Can I use, say, ...

Marko- > We are booting (note, this is not the same as executing) the device from > EMIF. We have an 16bit wide flash device...

Marko- > We are booting (note, this is not the same as executing) the device from > EMIF. We have an 16bit wide flash device attached to it. > > Regarding the CLKOUT issue see advisory DL_13: > > "...SYSR does not control CLKOUT divisor when

Hi Michael, Thank you for this information. I think that there is a problem in the PLL design of C5509A. It is good that I manage to get...

Hi Michael, Thank you for this information. I think that there is a problem in the PLL design of C5509A. It is good that I manage to get 186MHz stable operation as I described. Regards Mitko ----- Original Message ----- From: "Michael Schuster" To: ; Sent: Monday, June 26, 2006 5:05 PM Subject: Re: [c55x] Re: TMS320VC5509

Hi, I am trying to get familiar with the DSK5509a for a project. My first task was to write and read something(an integer, a string..) from...

Hi, I am trying to get familiar with the DSK5509a for a project. My first task was to write and read something(an integer, a string..) from the RAM memory, which i successfully did. Next, I have to do the same, but on the flash memory. Lately i have read a lot of articles, data manuals, and posts, about flashburn, EMIF, bootloaders, DMA ...etc and to be honest my head is mixed up right now. I ...

Hello Jeff, It is my board. The peripheral I mentioned is an image sensor which is a standard asynchronous memory. It is interesting that...

Hello Jeff, It is my board. The peripheral I mentioned is an image sensor which is a standard asynchronous memory. It is interesting that even without this sensor connected, the problem still exists. I think that the answer Andrej Novak gave me relates closely with my problem as I have observed strong correlation between enabling/disabling of the signal from "clockout " pin and th...

Hello, I start this month to use SDRAM (64MBit) on spaces CE0 CE1, but I have some problems. I write a program that use...

Hello, I start this month to use SDRAM (64MBit) on spaces CE0 CE1, but I have some problems. I write a program that use DMA transfers from internal DARAM to SDRAM trough the EMIF controller, my problem is that the system doesn't drive the addrs A[9..12].I can use

All, I'm working with Alex on this project. We've initilized the SDRAM registers according to the datasheet and to reference designs, and...

All, I'm working with Alex on this project. We've initilized the SDRAM registers according to the datasheet and to reference designs, and still nothing. What seems to happen is if you write a value to odd memory locations, the value sticks and you can read it back. But, ALL odd memory locations show the same value. This is with the chip in CE1 (which does seem to drop). The chip