Hello Group, I am having trouble understanding how to use the EMIF as a parallel port. I am attempting to interface an AD9857(ASIC) with a...

Hello Group, I am having trouble understanding how to use the EMIF as a parallel port. I am attempting to interface an AD9857(ASIC) with a TMS320C5510 (DSK). I have the EMIF signals routed to the expansion connector by pulling the DETECTn signal low. The ASIC requires a 14 bit data word from the DSP. The ASIC also maintains the data clock. I still have not been able to change the EMIF

I have a question about EMIF/HPI mode in C5507. It is true that we can not use HPI and EMIF at the same time, but the question is Can we use...

I have a question about EMIF/HPI mode in C5507. It is true that we can not use HPI and EMIF at the same time, but the question is Can we use HPI mode to boot up DSP when power up and then switch to EMIF mode by the application code after that? Thanks

Dear list, I have difficulties to boot up from SPI flash: IO4 goes down, DSP read data, but IO4 doesn't rise again. So DSP doesn't start to...

Dear list, I have difficulties to boot up from SPI flash: IO4 goes down, DSP read data, but IO4 doesn't rise again. So DSP doesn't start to execute. TI support told me EMIF.ARDY has to be pulled up to make boot loader successful. I think it's irrelevent since EMIF.ARDY is only for EMIF. I doublechecked the datasheet and see nothing relate EMIF.ARDY to SPI bootup. I know many people in this list...

In a master /slave application with two 5502-300Mhz, the master (via EMIF) read slave memory (throw its HPI). To speed-up the access, the EMIF is...

In a master /slave application with two 5502-300Mhz, the master (via EMIF) read slave memory (throw its HPI). To speed-up the access, the EMIF is configured in 32bit access to avoid double read. But the throughput is not very high, each read cycle (done by the master from DMA) is 300n. The EMIF configuration is : TA=0, read setup=1, read strobe=3, read hold=1. If I reduce read strobe to 2 it doesn...

Hi all, I am Unable Configure the EMIF using CSL Library.or Using Bios Cnfig file usin GUI configeration.. IF anyone knows...

Hi all, I am Unable Configure the EMIF using CSL Library.or Using Bios Cnfig file usin GUI configeration.. IF anyone knows about this pls Send me details .. 1>How to Configure EMIF using CSL Lib.. 2> How to Configure EMIF using Bios GUI Cnfigeration...

Hi, I want to do 32bit addressing in EMIF CE2. I have defined MYTPE for 32bit . EMIF space 2 starts with word address 0x40 0000. Now I am not...

Hi, I want to do 32bit addressing in EMIF CE2. I have defined MYTPE for 32bit . EMIF space 2 starts with word address 0x40 0000. Now I am not sure of which address will be given for 32bit addressing- whether the same 0x40 0000 or it should be divided by 2 again for 32 bit addressing i.e starting with 0x20 0000. Also what abt address bus A0 and A1- should they be unused as for 32bit address...

hi; When I set dma for receive and transmit channels and program the audio codec registers for aic23 on DSK5510 its emif works(I can write and...

hi; When I set dma for receive and transmit channels and program the audio codec registers for aic23 on DSK5510 its emif works(I can write and read from 0x550000 and see CE0 pules on oscope) but when I don't set them EMIF doesn't work. Do you know why? sincerely

Hello All, My conclusions on the EMIF problems due to PLL instability: 1. The load on clockout pin influences the C5509A PLL stability...

Hello All, My conclusions on the EMIF problems due to PLL instability: 1. The load on clockout pin influences the C5509A PLL stability significantly in case clockout signal is enabled (in both EBSR and ST3_55 registers)! 2. In case clockout signal is disabled the load on clockout pin doesn't influence the PLL stability anymore. 3. The EMIF of C5509A is not stable (at CPU clock around ...

Hi Jeff > With 5502 we're running 300 MHz and EMIF (SRAM) at 100 MHz (I think, have > to ask our engineers) and that seems to be stable. I...

Hi Jeff > With 5502 we're running 300 MHz and EMIF (SRAM) at 100 MHz (I think, have > to ask our engineers) and that seems to be stable. I wonder if the EMIF > issues you mention also exist on 5510... Ok I see. Yes I am also wondering if 5510 has the same PLL design. The strange thing is that what I am reporting is very basic and it must have been observed by all. Best Regards Mit

hi, hope you know the problem with the C5501/5502 emif wherin it will always do a 32 bit asynchronous memory read...

hi, hope you know the problem with the C5501/5502 emif wherin it will always do a 32 bit asynchronous memory read irrespective of your mtype configuration. further, the asynchronous memory writes works as expected.refer the latest emif document spru621e for details.

Hi everyone, We are currently upgrading our product, going from 5410A to 5509A. I do need to use the EMIF to load my...

Hi everyone, We are currently upgrading our product, going from 5410A to 5509A. I do need to use the EMIF to load my code from flash, and i also need to use the HPI to communicate with the Host. The only problem, is that these 2 ports (EMIF and HPI)

All- We are doing a C5502 design, with emphasis on low cost. One issue that we still have not resolved is EMIF clock rate -- we...

All- We are doing a C5502 design, with emphasis on low cost. One issue that we still have not resolved is EMIF clock rate -- we would normally use 7 or 8 nsec external SRAM, and try to get as close to 100 MHz EMIF clock rate as possible. But C5502 running at 300 MHz naturally

Hi, we've prooved (unfortunately we didn't see the spra925 Appendix before) that the emif of a 5501 device will make an async read acess to...

Hi, we've prooved (unfortunately we didn't see the spra925 Appendix before) that the emif of a 5501 device will make an async read acess to the emif only 1 per 18 cpu cycles. So a really fast read from the async interface is not possible. tI told us, the 5503/07/09 is much faster in this matter. Can someone approve this? How fast can you achieve with that devices? Thanks i

Hi Dileepan, I am working with TMS320C5509A emif and facing a similar problem. When I write address for CE spaces no Chip select is...

Hi Dileepan, I am working with TMS320C5509A emif and facing a similar problem. When I write address for CE spaces no Chip select is generated. By default CE signal for CE space CE1 is generated for any address. I am writing address as mentioned by you. Also if I write statement *(int*)0x400000 = 0xFFFF; // CE space 2 as I am using in word mode config where should i be able to see the data ...

Hi, We've been developing code on a custom PCB for the 5502 chip. We realized we needed a port expander, so we made a revision to our custom...

Hi, We've been developing code on a custom PCB for the 5502 chip. We realized we needed a port expander, so we made a revision to our custom board. However, now we are not able to configure the PLL to get a CPU clock speed above 132 MHz AND have functional SDRAM interface or peripherals. The emulation freezes when the EMIF is utilized if PLL_DIV3 is not set to 0x8003, regardless of clock ...

Hi all, I'd like to do periodic DMA transmission from DARAM to EMIF at 1kHz with the C5509A. Therefore I use a timer and I perform a...

Hi all, I'd like to do periodic DMA transmission from DARAM to EMIF at 1kHz with the C5509A. Therefore I use a timer and I perform a DMA_start inside of the timer's ISR. When I look at the signals at the EMIF, it seems that very often the DMA doesn't start and that this happens very irregularly. Just to complete the picture: if i symbolize successful transmissions with a T and unsuccessful...

Hi All, I am working on TMS320C55 (OMAP5910). I need to change some registers for EMIF. I do know 16-bit addresses for my registers but I...

Hi All, I am working on TMS320C55 (OMAP5910). I need to change some registers for EMIF. I do know 16-bit addresses for my registers but I cannot write them using CCS. I need to know 32-bit address of that registers so I could write new values in that registers. I do not know 32-bit addresses for my registers but I cannot find any useful documentation that describes necessary addresses. Does...

Hello, i have spent several hours trying to get my Flash Memory (AT49LV1024, 1Mbit) running on EMIF. My Configuration...

Hello, i have spent several hours trying to get my Flash Memory (AT49LV1024, 1Mbit) running on EMIF. My Configuration is: EMIF_FSET(EGCR,MEMFREQ,4); //MEMFREQ 1/16 CPU EMIF_FSET(EGCR,MEMCEN,1); //MEMClock on CLKMEM EMIF_FSET(EGCR,NOHOLD,0); //MEMClock on CLKMEM EMIF_FSET(CE21,MTYPE,1); //16 bit async EMIF_FSET(CE21,RDSETUP,1); //RD Setup Clock Time EMIF_FSET(CE21,RDSTROBE,17); //RD...

Hello, I'm trying to change parallel bus to EMIF mode, but I don't know how to do it from source code. It goes to HPI mode when because of...

Hello, I'm trying to change parallel bus to EMIF mode, but I don't know how to do it from source code. It goes to HPI mode when because of BOOT3 (IO.0) is 0 during power up (bootloader uses serial EEPROM). I'm trying to write EBSR register (0x6c00) but it doesn't work. Can it be done dynamically (datasheet doesn't recommend that) and how? thanks, Janne

Dear All, Using 5510 dsk, Spectrum Digital, In a hurry to drive EMIF bypassing DSP/BIOS? but I can't see the CE pin changing in the...

Dear All, Using 5510 dsk, Spectrum Digital, In a hurry to drive EMIF bypassing DSP/BIOS? but I can't see the CE pin changing in the write operation: ?? ?Here is main source file: ?? ?======================= #include #include #include #include #include EMIF_Config emifCfg0 = { ??? 0x022F,??????? /*? Global Control Register??