Sigma-delta modulation (also called delta-sigma modulation) is a technique for converting analog signals to digital (or digital to analog) by encoding amplitude information in the density of a high-frequency, low-resolution (often 1-bit) bit stream, relying on oversampling and noise shaping to push quantization noise out of the signal band.
In practice
Sigma-delta ADCs are a dominant architecture wherever high resolution (16–24 bits) is needed at moderate bandwidths, such as audio, industrial weight scales, pressure sensors, and precision voltage measurement, though SAR and pipeline architectures may be preferred when speed, latency, or other constraints dominate. Chips like the ADS1256 (24-bit, TI), MAX11254 (24-bit, Maxim), and the built-in sigma-delta ADC on the STM32H7 series illustrate the range from external precision converters to integrated peripherals. The tradeoff is conversion latency: the decimation filter that follows the modulator introduces group delay ranging from tens to thousands of output samples depending on filter order and decimation ratio.
The modulator oversamples the input at a rate many times the Nyquist rate (oversampling ratios of 64x to 512x are common for many designs, though the practical range varies with modulator order, target resolution, and output data rate) and applies a feedback loop with an integrator and quantizer. The feedback loop shapes quantization noise so that most of it falls at high frequencies, far above the signal band. A digital decimation filter then low-pass filters and downsamples the bit stream to produce a high-resolution output word at the final output data rate. Filter design for the decimation chain is non-trivial; using multiple cascaded stages (for example a CIC followed by a halfband FIR) is a common optimization covered in depth in "Multi-Decimation Stage Filtering for Sigma Delta ADCs: Design and Optimization."
Sigma-delta DACs operate in the reverse direction: a high-resolution digital word is converted to a high-rate low-resolution (often 1-bit or few-bit) stream by an interpolation filter and a digital modulator, and the resulting stream is smoothed by an analog reconstruction filter. The behavior of a simple sigma-delta DAC followed by an RC filter can be modeled and simulated as described in "Model a Sigma-Delta DAC Plus RC Filter," which is useful for verifying the reconstruction filter cutoff and settling behavior before committing to hardware.
A key pitfall in embedded designs is misunderstanding the relationship between output data rate and effective bandwidth. The output data rate on a sigma-delta ADC datasheet is the decimated sample rate; the usable analog input bandwidth is typically a fraction of that rate, determined by the decimation filter's passband response rather than the decimation ratio alone. Reading the filter frequency response curves in the datasheet is essential for applications with signals near the edge of the passband, where droop and phase nonlinearity can affect measurement accuracy.
Discussed on DSPRelated
Frequently asked
Why do sigma-delta ADCs report high bit depths (e.g., 24 bits) when the internal quantizer is often just 1 bit?
The 1-bit quantizer has very coarse resolution on its own, but the combination of heavy
oversampling and noise shaping redistributes quantization noise away from the signal band. After the
decimation filter removes the out-of-band noise, the remaining in-band noise floor is low enough to support effective resolutions of 20-24 bits. The achievable resolution still depends on the oversampling ratio, modulator order, and analog front-end noise.
What is noise shaping and why does it matter?
Noise shaping is the process by which the feedback loop in a sigma-delta modulator causes quantization noise to be spectrally concentrated at high frequencies rather than spread uniformly across the band. A first-order modulator achieves approximately 9 dB improvement in
SNR per doubling of the
oversampling ratio under ideal conditions (compared to 3 dB for simple oversampling alone); real implementations can deviate due to analog noise and other nonidealities. Higher-order modulators achieve steeper noise shaping but require careful stability analysis, since higher-order loops can become conditionally stable depending on the specific topology and coefficient choices.
What is the decimation filter, and does it affect latency?
The
decimation filter is a digital
low-pass filter that removes the high-frequency shaped noise and downsamples the high-rate bit stream to the final output word rate. It is the primary contributor to latency, though the modulator pipeline and any additional digital filtering can also play a role. As a rule of thumb, a sinc3 (SINC^3) filter common in many
ADC chips introduces a settling time of approximately 3/f_output before a new reading is fully settled after an input step, though the exact settling behavior varies across parts and output data-rate settings. Applications that multiplex many channels rapidly (such as scanning multiple sensors) must account for this settling time or accept errors from incomplete settling.
When should I choose a sigma-delta ADC over a SAR ADC?
Sigma-delta ADCs are generally preferred when resolution above ~16 bits is needed and conversion speed can be moderate (typically up to tens of kilosamples per second for high-resolution modes, though audio-grade parts reach ~192 kSps, and some sigma-delta parts support higher rates at reduced resolution). SAR ADCs are preferred when fast, simultaneous, or high-throughput sampling is needed (hundreds of kSps to MSPS range), or when very low latency per conversion is required. The speed-resolution boundary is not sharp and depends on the specific parts being compared. Many embedded designs use both: SAR for fast control-loop feedback and sigma-delta for precision DC or low-frequency measurements.
Can sigma-delta modulation be implemented in firmware on an MCU without a dedicated ADC?
Yes. A common technique on MCUs without a built-in sigma-delta
ADC is to use a toggled GPIO or PWM output as a coarse 1-bit stimulus, combined with an external RC network and a comparator or fast GPIO input, to approximate a first-order modulator loop in software or hardware. The bit stream is then decimated in firmware. Resolution is limited by the MCU's GPIO toggle rate and timer jitter, but this approach has been used on Cortex-M0 and AVR-class parts to achieve 10-12 effective bits at audio rates with minimal external components.
Differentiators vs similar concepts
The terms sigma-delta and delta-sigma refer to the same modulation technique; usage varies by region and author with no meaningful technical distinction. This is distinct from simple delta modulation, which tracks only the change (delta) between successive samples using a fixed step size and has no integrator-based noise shaping loop, resulting in lower dynamic range and slope-overload distortion not present in sigma-delta designs.
