Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA
This update shows a working integration between Pyfda and MyHDL using a compact API that passes fixed-point coefficients, stimulus data, and returns simulated filter responses. It walks through two usage styles, constructor-based and setter-method-based, and demonstrates a Pyfda workflow from specs to MyHDL simulation and plotting. Future plans include HDL code generation and API extension as filters grow.
Project update-1 : Digital Filter Blocks in MyHDL and their integration in pyFDA
By week 5 the project delivered parameterized MyHDL implementations of multiple digital filter topologies and started integration with PyFDA. The post walks through a behavioral direct-form I FIR, cascaded second-order-section implementations for FIR and IIR using structural modeling, and a parallel IIR design that concatenates per-section outputs for final summation. All designs infer order and coefficients from PyFDA, with examples in the filter-blocks repository.
Linear Feedback Shift Registers for the Uninitiated, Part XVI: Reed-Solomon Error Correction
Jason Sachs demystifies Reed-Solomon codes with hands-on examples and pragmatic tips for embedded engineers. The article shows why RS encoding is just polynomial division in GF(2^m), why decoding is mathematically heavier, and how to implement encoders in Python and in C-friendly form using LFSRs and table-driven methods. Read this for working code, generator-polynomial examples, and an embedded-minded view of RS practicalities.
Linear Feedback Shift Registers for the Uninitiated, Part XV: Error Detection and Correction
CRCs and Hamming codes look a lot less magical when you view them as redundancy with a purpose. Jason Sachs walks from parity bits and checksums into finite-field polynomial arithmetic, then shows how CRCs map cleanly onto LFSRs and how Hamming codes use syndromes to locate single-bit errors. It is a practical tour of error detection and correction, with enough worked examples to make the theory feel usable.
Who else is going to Sensors Expo in San Jose? Looking for roommate(s)!
Stephane Boucher is heading to Sensors Expo in San Jose for the first time, and he is bringing cameras to capture demos and build a highlights video. He is also looking for roommates for a roomy Airbnb near the convention center, plus local tips for making the most of a free day in the Bay Area. If you are attending, there is also a registration discount code and a VIP pass giveaway in the mix.
Digital PLL's, Part 3 -- Phase Lock an NCO to an External Clock
Phase-locking a numerically controlled oscillator to an external clock that is unrelated to system clocks is practical and largely unexplored. Neil Robertson presents a time-domain digital PLL that converts the ADC-sampled clock into I/Q with a Hilbert transformer and measures phase error with a compact complex phase detector. The post shows loop-filter coefficient formulas and simulations that reveal how ADC quantization and Gaussian clock noise map into NCO phase noise and how loop bandwidth shapes the result.
Project introduction: Digital Filter Blocks in MyHDL and their integration in pyFDA
Sriyash Caculo is building a bridge between filter design and hardware by implementing digital filter blocks in MyHDL and integrating them with PyFDA as part of a Google Summer of Code project. The work aims to convert PyFDA floating point designs into fixed point MyHDL blocks that automatically generate VHDL or Verilog, with tests and tutorials to ensure correctness and usability.
Two Easy Ways To Test Multistage CIC Decimation Filters
Rick Lyons shows that you can validate multistage CIC decimation filters with just two obvious tests, no elaborate spectral setup required. Apply a unit-sample impulse to check a combinatorial yout(1) value when D ≥ S, or feed an all-ones step to confirm an S-sample transient followed by a DS steady state; the Appendix ties both checks to Pascal's triangle and binomial math.
ADC Clock Jitter Model, Part 2 – Random Jitter
Neil Robertson shows how to simulate ADC sample-clock random jitter in Matlab, moving from band-limited Gaussian noise to wideband and close-in phase noise. The post highlights practical artifacts such as aliasing of wideband clock noise, the 20*log10 dependence of jitter sidebands on input frequency, and why cubic interpolation plus a custom noise_filter produces accurate rms and spectral results engineers can trust.
Take Control of Noise with Spectral Averaging
Spectral averaging turns noisy FFT outputs into repeatable, measurable spectra by trading time for noise control. This post explains the practical difference between RMS averaging, which reduces variance without changing the noise floor, and vector averaging, which can lower the noise floor but requires phase-coherent, triggered inputs. It also shows how linear and exponential weighting affect reaction time for live displays and measurement accuracy.
A Recipe for a Basic Trigonometry Table
Cedron Dawg walks through building a degree-based sine and cosine table from first principles, showing both recursive and multiplicative complex-tone generators. The article highlights simple drift-correction tricks such as mitigated squaring and compact normalization, gives series methods to compute one-degree and half-degree values, and includes practical C code that ties the table to DFT usage and frequency estimation.
Compute Modulation Error Ratio (MER) for QAM
Neil Robertson shows how to define and compute Modulation Error Ratio (MER) for QAM using a simplified baseband model and decision-slice errors. The post derives per-symbol and averaged MER formulas, explains when MER tracks carrier-to-noise ratio under AWGN and matched root-Nyquist filters, and provides example Pav values for QAM-16 and QAM-64 plus a Matlab script and practical tips.
Design a DAC sinx/x Corrector
Neil Robertson provides a compact Matlab function and coefficient tables for designing linear-phase FIR sinx/x correctors to undo the DAC sinc roll-off. The post explains the sinc_corr(ntaps,fmax,fs) call, shows worked examples with ntaps=5 and different fmax values, and demonstrates fixed-point quantization including a k=512 example and CSD digit guidance. Practical notes cover corrector gain and input back-off to avoid clipping.
Went 280km/h (174mph) in a Porsche Panamera in Germany!
A week at SEGGER’s headquarters in Germany turned into more than a video shoot, it became a look inside a company that clearly runs on passion, trust, and a lot of teamwork. Stephane Boucher also gets an unforgettable autobahn ride in a Porsche Panamera, hitting 280 km/h along the way. Between interviews, B-roll, and a 25th anniversary celebration, he comes away impressed by both the people and the pace.
Design study: 1:64 interpolating pulse shaping FIR
Markus Nentwig presents a practical 1:64 root-raised cosine interpolator built from cascaded FIR stages that slashes computational cost. By separating pulse shaping from rate conversion, designing each interpolator to suppress only known alias bands, and equalizing the pulse shape, the design achieves just 4.69 MACs per output, roughly 12 percent of a straight polyphase implementation while meeting EVM targets.
Simulink-Simulation of SSB demodulation
This post walks through Simulink models that implement SSB demodulation and modulation, using Richard Lyons' phasing method as a foundation. It shows practical models for simple carrier multiplication and for the phasing method with cosine and -sin paths plus Hilbert filtering, and it highlights sampling, decimation, filter choices, and delay alignment to make the techniques work in simulation.
Signal Processing Summit - Cancellation Policy
The post announces a flexible cancellation policy for the inaugural Signal Processing Summit, an intimate DSP event limited to 70 seats and scheduled in Silicon Valley this October. It explains refundable options designed to give attendees confidence when registering early: a full refund minus a $95 processing fee for cancellations before the end of September, a 50% refund for cancellations in October before October 6, and no refunds after that date. The policy is positioned to help prospective attendees lock in the Early Bird rate, secure discounted hotel accommodations, and plan travel with reduced risk. The announcement frames the policy as a way to remove barriers to commitment and encourages readers who have been undecided to register now and attend the Summit.
Learn About Transmission Lines Using a Discrete-Time Model
A simple discrete-time approach makes lossless transmission-line behavior easy to simulate and visualize. The post introduces MATLAB functions tline and wave_movie to model uniform lossless lines with resistive terminations, compute time and frequency responses, and animate travelling waves. A microstrip pulse example shows how reflections produce ringing and how source matching nearly eliminates it, making this a practical learning tool.
DSP Algorithm Implementation: A Comprehensive Approach
This post lays out a practical pathway for taking DSP algorithms from high level simulation to production hardware, comparing GPP, DSP, FPGA and ASIC platforms. It presents a stepwise methodology starting with nested loop programs, then exposing parallelism with data flow graphs, using SystemC transaction level modeling to bridge to Verilog or VHDL, and explains why that flow speeds design and simulation.
Some Thoughts on Sampling
Sampling's 1/Ts amplitude factor is not a paradox but a consequence of axis scaling and impulse density, once you view the units correctly. This post walks through impulse trains in continuous and discrete time, uses DFT examples and Parseval's relation, and shows how downsampling and time scaling produce the familiar spectral replicas and their amplitudes. The geometry of the axes resolves the confusion.
Should DSP Undergraduate Students Study z-Transform Regions of Convergence?
Rick Lyons argues z-transform regions of convergence are mostly a classroom abstraction with little practical use for real-world DSP engineers. For all stable LTI impulse responses encountered in practice the ROC includes the unit circle, so DTFT and DFT exist and ROC analysis rarely affects implementation. He notes digital oscillators are a notable exception, and suggests reallocating classroom time to more practical engineering topics.
Compute Modulation Error Ratio (MER) for QAM
Neil Robertson shows how to define and compute Modulation Error Ratio (MER) for QAM using a simplified baseband model and decision-slice errors. The post derives per-symbol and averaged MER formulas, explains when MER tracks carrier-to-noise ratio under AWGN and matched root-Nyquist filters, and provides example Pav values for QAM-16 and QAM-64 plus a Matlab script and practical tips.
Time-Domain Periodicity and the Discrete Fourier Transform
Finite-length observation windows change how tones appear in a DFT, and Eric Jacobsen shows how the convolution theorem explains the familiar sin(x)/x main lobe and sidelobes. He contrasts two consistent viewpoints: viewing the DFT as a windowed signal convolved with the window transform, or as the transform of a periodically repeated sequence. Practical tips on zero-padding, bin spacing, and phase effects help avoid common misinterpretations.
How the Cooley-Tukey FFT Algorithm Works | Part 4 - Twiddle Factors
The beauty of the FFT algorithm is that it does the same thing over and over again. It treats every stage of the calculation in exactly the same way. However, this. “one-size-fits-all” approach, although elegant and simple, causes a problem. It misaligns samples and introduces phase distortions during each stage of the algorithm. To overcome this, we need Twiddle Factors, little phase correction factors that push things back into their correct positions before continuing onto the next stage.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
How precise is my measurement?
Precision is quantifiable, not guesswork. This post walks through practical, measurement-oriented statistics you can apply to static or dynamic signals to answer the question, "How precise is my measurement?" It focuses on using multiple samples, checking distribution assumptions, and constructing confidence intervals and levels so you can trade measurement time for a desired precision.
Instantaneous Frequency Measurement
Measuring carrier frequency quickly and with minimal data matters in radar and signal characterization. Parth Vakil explains the delay-and-multiply instantaneous frequency measurement technique, shows how analytic signals and multiple delays resolve the 2π ambiguity, and demonstrates noise, phase-wrapping, and interferer effects using MATLAB code. He also outlines practical mitigations like phase unwrapping and channelization.
The DFT of Finite-Length Time-Reversed Sequences
Rick Lyons digs into a surprisingly under-documented corner of DSP, showing how finite-length time reversal changes a sequence's DFT. The post distinguishes flip and circular time-reversal, gives closed-form DFT relationships, and explains why modulo N arithmetic matters. Engineers get ready-to-use tables and derivations that clarify when and how time reversal affects spectral analysis.
Design study: 1:64 interpolating pulse shaping FIR
Markus Nentwig presents a practical 1:64 root-raised cosine interpolator built from cascaded FIR stages that slashes computational cost. By separating pulse shaping from rate conversion, designing each interpolator to suppress only known alias bands, and equalizing the pulse shape, the design achieves just 4.69 MACs per output, roughly 12 percent of a straight polyphase implementation while meeting EVM targets.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
