Evaluate Window Functions for the Discrete Fourier Transform
Spectral leakage makes DFTs of continuous sinewaves misleading, and windowing is the practical workaround. This post supplies Matlab code to plot spectra of windowed sinewaves and compute figures of merit, so you can compare windows such as flattop and Chebyshev. See how sidelobe level, mainlobe bandwidth, processing loss, noise bandwidth, and scallop loss trade off to guide your window choice.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Polar Coding Notes: A Simple Proof
Lyons Zhang presents a compact, elementary derivation of channel polarization for binary-input discrete memoryless channels. The note leverages Mrs. Gerber's Lemma to bound conditional entropies and follows the Alsan-Telatar averaging argument to show mediocre channels vanish. The proof sidesteps martingale convergence and recovers the standard result that the fraction of good channels approaches the channel capacity.
Polar Coding Notes: Channel Combining and Channel Splitting
Lyons Zhang walks through the core algebra of polar coding, showing how channel combining builds the vector channel W_N from N copies of a binary-input DMC using the polar transform G_N = B_N F^{⊗n}. The notes then define channel splitting, derive the coordinate-channel transition probabilities from the chain rule, and present the recursive formulas that let you compute W_{2N}^{(2i-1)} and W_{2N}^{(2i)} from W_N^{(i)}.
Project Report : Digital Filter Blocks in MyHDL and their integration in pyFDA
This Summer of Code project shows how to move from Python filter design to synthesizable HDL by building a MyHDL "filter-blocks" package and connecting it to PyFDA. The author implemented direct form I FIR and IIR blocks, added an API, tests, tutorials, and PyFDA export to VHDL and Verilog. The report also highlights practical fixed-point design choices and remaining work such as second-order sections.
Sensors Expo - Trip Report & My Best Video Yet!
Stephane Boucher turns a first-time Sensors Expo visit into a fun travelogue and a polished conference highlights video. He mixes candid trip anecdotes from Moncton to San Jose, electric-scooter discoveries, Santa Cruz detours, Airbnb tips, and on-the-floor expo footage. The post culminates in what he calls his best highlights reel yet, plus a follow-up video focused on embedded and IoT.
Design a DAC sinx/x Corrector
Neil Robertson provides a compact Matlab function and coefficient tables for designing linear-phase FIR sinx/x correctors to undo the DAC sinc roll-off. The post explains the sinc_corr(ntaps,fmax,fs) call, shows worked examples with ntaps=5 and different fmax values, and demonstrates fixed-point quantization including a k=512 example and CSD digit guidance. Practical notes cover corrector gain and input back-off to avoid clipping.
Off Topic: Refraction in a Varying Medium
Cedron Dawg derives a compact vector differential equation for a point particle moving through a smoothly varying refractive medium using the Euler-Lagrange variational method. By introducing a log refractive index called "fluff density," the paper expresses acceleration purely in terms of the fluff gradient and velocity, then explores curvature, superposition, and point-source capture radii with simple closed-form results.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Project update-2 : Digital Filter Blocks in MyHDL and their integration in pyFDA
This update shows a working integration between Pyfda and MyHDL using a compact API that passes fixed-point coefficients, stimulus data, and returns simulated filter responses. It walks through two usage styles, constructor-based and setter-method-based, and demonstrates a Pyfda workflow from specs to MyHDL simulation and plotting. Future plans include HDL code generation and API extension as filters grow.
Spline interpolation
Markus Nentwig provides a cookbook for segmented cubic spline interpolation that turns scattered or noisy data into efficient fixed-point functions. The article shows how to build third-order polynomial segments with explicit value and slope control via basis functions, solve scaling factors by least-squares in Octave/Matlab, and export coefficients for Verilog RTL evaluation using the Horner scheme and practical fixed-point tips.
Accurate Measurement of a Sinusoid's Peak Amplitude Based on FFT Data
Measuring a sinewave's peak from FFT data can be severely biased by scalloping loss, producing errors up to 36.3 percent. Rick Lyons demonstrates how to apply a flat-top window via frequency-domain convolution to the FFT bins, cutting maximum amplitude error to about 0.02 dB compared with 3.9 dB for rectangular windows. The post includes Matlab code and practical caveats for reliable use.
The DSP Online Conference - Right Around the Corner!
Three months after a forum post, Stephane Boucher and Jacob Beningo pulled together the DSP Online Conference, a two-day virtual event featuring 14 talks from leading DSP experts. Most sessions are 30 to 60 minutes with a 30-minute Zoom Q&A, while extended deep dives from speakers like fred harris are included. Registered attendees get one-year on-demand access, and free or reduced passes are available.
The DFT Magnitude of a Real-valued Cosine Sequence
Rick Lyons proves a simple but often-missing result: the N-point DFT peak magnitude of a real cosine with an integer number of cycles equals A·N/2. He uses Euler's formula and geometric-series summation, shows a neat shortcut that avoids l'Hôpital's rule, and connects the math to practical fixed-point FFT sizing and overflow prevention on two's-complement hardware. The post also notes conjugate symmetry and the same result for sine inputs.
Least-squares magic bullets? The Moore-Penrose Pseudoinverse
Markus Nentwig walks through a practical way to remove power-line hum from measurements using the Moore-Penrose pseudoinverse. He builds a harmonic basis, computes pinv(basis) to get least-squares coefficients, and reconstructs and subtracts the hum, with a ready-to-run Matlab example. The post highlights limits and performance: basis-like signal components will be removed, and accuracy improves with the square root of sample count.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
Two jobs
Stephane Boucher explains why EmbeddedRelated went quiet for a few months after a volunteer project demanded more of his time. He and his wife organized a clown-gymnastics show with 15 kids, sold more than 700 of 800 tickets, and raised $2,700 for the Tree of Hope. Now the shows are done and he plans to resume regular posting with new site features.
Recruiting New Bloggers!
EmbeddedRelated is expanding its blogging team, and Stephane Boucher is inviting engineers, students, hobbyists, and researchers to contribute. He points to the success of earlier contributors and says the community has already read their articles more than 1,250,000 times. If you have knowledge to share, this post explains how to pitch a topic and get started.
Find Aliased ADC or DAC Harmonics (with animation)
If a sinewave drives an ADC or DAC, device nonlinearities create harmonics that can fold back as aliases above Nyquist. This post shows a simple Matlab model, using an NCO, a static nonlinearity, and a DFT to generate spectra and reveal aliased harmonics, with animated illustrations to make aliasing intuitive. The approach works for both ADC and DAC measurement setups and highlights realistic effects like quantization noise.
Multi-Decimation Stage Filtering for Sigma Delta ADCs: Design and Optimization
A Matlab toolbox streamlines the design and optimization of multi-stage decimation filters for sigma-delta ADCs. MSD-toolbox automates stage-count and decimation-factor selection, generates Parks-McClellan equiripple FIR coefficients, and iteratively selects coefficient quantization to meet in-band noise constraints. It accepts sigma-delta bitstream stimuli for spectral and intra-stage analysis, includes cost estimation routines, and is published open-source on MathWorks with examples and a dissertation reference.
Correcting an Important Goertzel Filter Misconception
A common claim says the Goertzel algorithm is marginally stable and prone to numerical errors. Rick Lyons shows that the usual second-order Goertzel filter has conjugate poles exactly on the unit circle, so pole placement alone does not make it unstable. The practical limits are coefficient quantization, which reduces frequency precision, and accumulator overflow for very large N.
Demonstrating the Periodic Spectrum of a Sampled Signal Using the DFT
This post makes a basic DSP principle tangible by computing the DFT over an extended set of bins and plotting the results. It demonstrates that a sampled signal's spectrum repeats every sampling rate, explains the k-to-frequency mapping, and contrasts common bin ranges such as 0..N-1 and -N/2..N/2-1. The write-up also highlights symmetry for real sequences and recommends using the FFT for efficiency.
New Comments System (please help me test it)
DSPRelated just got a practical upgrade, Stephane Boucher has released a new comments system built from his earlier forum work. It supports drag-and-drop or Insert Image uploads, MathML, TeX and ASCIImath rendered by MathJax, syntax-highlighted code via highlight.js, and in-place editing and deletion of comments. Improved email notifications alert authors and commenters to replies, and readers are invited to post test comments and report problems.
How precise is my measurement?
Precision is quantifiable, not guesswork. This post walks through practical, measurement-oriented statistics you can apply to static or dynamic signals to answer the question, "How precise is my measurement?" It focuses on using multiple samples, checking distribution assumptions, and constructing confidence intervals and levels so you can trade measurement time for a desired precision.
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
Should DSP Undergraduate Students Study z-Transform Regions of Convergence?
Rick Lyons argues z-transform regions of convergence are mostly a classroom abstraction with little practical use for real-world DSP engineers. For all stable LTI impulse responses encountered in practice the ROC includes the unit circle, so DTFT and DFT exist and ROC analysis rarely affects implementation. He notes digital oscillators are a notable exception, and suggests reallocating classroom time to more practical engineering topics.
DAC Zero-Order Hold Models
This article provides two simple time-domain models of a DAC’s zero-order hold. These models will allow us to find time and frequency domain approximations of DAC outputs, and simulate analog filtering of those outputs. Developing the models is also a good way to learn about the DAC ZOH function.
A Simple Complex Down-conversion Scheme
Rick Lyons shows a compact way to turn a real bandpass signal centered at ±fs/4 into a complex, zero-centered analytic signal. The trick uses a delay, a Hilbert transform filter, and a 4:1 downsample, with a small compensation filter to widen the usable passband. He also points out a no-multiplier implementation using shift-and-add coefficients, or a higher-attenuation version with two multiplies per output sample.
Discrete Wavelet Transform Filter Bank Implementation (part 1)
David Valencia walks through a practical implementation of discrete wavelet transform filter banks, focusing on cascading branches and efficient equivalent filters. He contrasts DWT and DFT resolution behavior and shows how cascading the low-pass branch sharpens frequency division while the high-pass path remains unchanged. Code pointers and a preview of formfilters() demonstrate how to compute only the needed samples by combining filters with upsampling.
Half-band filter on Xilinx FPGA
Lyons Zhang shows a practical, high-throughput implementation of a symmetric systolic half-band FIR on Xilinx FPGAs using DSP48 slices. The post includes a two-channel interleaved downsample-by-2 Verilog module, pipeline mapping to DSP48, and a symmetric rounding trick to reduce the DC shift from truncation. It highlights performance-and-latency tradeoffs and gives working code you can drop into a Spartan-6 style flow.
