Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
Feedback Controllers - Making Hardware with Firmware. Part 9. Closing the low-latency loop
This article demonstrates combining DSP and feedback-control on an Intel Cyclone floating-point FPGA to build low-latency closed-loop circuit emulators and controllers. Using a single floating-point biquad at 1.6 Msps, an IFFT multi-tone 4.096 ms capture for wideband measurement, and MATLAB references for verification, the author achieves sub-nanosecond timing insight and applies DSP phase compensation to cancel about 100 pF of PCB parasitics.
Design IIR Filters Using Cascaded Biquads
High-order IIR filters are numerically sensitive, especially at low cutoff frequencies. This article shows how to implement a Butterworth lowpass as a cascade of second-order biquads, deriving the per-section coefficient formulas and giving a Matlab biquad_synth example. It explains computing denominator coefficients from pole pairs, using b = [1 2 1] with K = sum(a)/4 for unity DC gain, and highlights reduced quantization sensitivity.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
An Efficient Linear Interpolation Scheme
A simple trick slashes the cost of linear interpolation to at most one multiply per output sample, and often to none. The post shows a zero-order-hold based network that preserves input samples, has a short L-1 transient, and lets 1/L scaling be implemented as a binary shift when L is a power of two. It also gives a fixed-point layout that moves scaling to the end to reduce quantization distortion.
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This installment digs into practical FPGA choices and board-level issues for a low-latency, floating-point feedback controller. It compares a Cyclone V implementation against an older SHARC-based design, quantifies the tradeoff between raw DSP resources and cycle latency, and calls out Gotchas found on the BeMicro CV A9 evaluation card. Engineers get concrete prompts for where to optimize: clocking, DSP-block use, I/O standards, and algorithm partitioning.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...
Canonic Signed Digit (CSD) Representation of Integers
Canonic Signed Digit (CSD) encoding slashes the number of nonzero bits in integer coefficients, enabling multiplierless FIR filters implemented with shifts and adds. This post uses MATLAB code to demonstrate CSD rules, show how negative values work, and plot the distribution of signed digits as bit width changes. It finishes with practical techniques to minimize signed digits per coefficient for area and power efficient filter designs.
Matlab Code to Synthesize Multiplierless FIR Filters
Learn how to build multiplierless FIR lowpass filters in Matlab using Canonic Signed-Digit coefficients. The post explains converting Parks-McClellan floating-point taps to scaled integers, then to exact CSD digits, and includes two m-files that search maintap scaling to minimize signed digits while preserving the filter response. Practical notes cover external gain compensation, the 2/3 full-scale CSD limit, and sensitivity to pass/stop edges.
Design IIR Filters Using Cascaded Biquads
High-order IIR filters are numerically sensitive, especially at low cutoff frequencies. This article shows how to implement a Butterworth lowpass as a cascade of second-order biquads, deriving the per-section coefficient formulas and giving a Matlab biquad_synth example. It explains computing denominator coefficients from pole pairs, using b = [1 2 1] with K = sum(a)/4 for unity DC gain, and highlights reduced quantization sensitivity.
Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
An Efficient Linear Interpolation Scheme
A simple trick slashes the cost of linear interpolation to at most one multiply per output sample, and often to none. The post shows a zero-order-hold based network that preserves input samples, has a short L-1 transient, and lets 1/L scaling be implemented as a binary shift when L is a power of two. It also gives a fixed-point layout that moves scaling to the end to reduce quantization distortion.
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
Canonic Signed Digit (CSD) Representation of Integers
Canonic Signed Digit (CSD) encoding slashes the number of nonzero bits in integer coefficients, enabling multiplierless FIR filters implemented with shifts and adds. This post uses MATLAB code to demonstrate CSD rules, show how negative values work, and plot the distribution of signed digits as bit width changes. It finishes with practical techniques to minimize signed digits per coefficient for area and power efficient filter designs.
A poor man's Simulink
Markus Nentwig built a compact glue layer that embeds NGSPICE into Octave to cosimulate continuous-time circuits and digital control. The article walks through an RC lowpass example, the MEX-based Octave interface, and the breakpoint-driven cosimulation flow, showing how adaptive SPICE integration handles asynchronous and time-triggered events. It presents a practical, low-cost alternative to Simulink for tightly coupled analog-digital system design.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
Finding the Best Optimum
Optimization is seductive but often misleading, especially when mathematical models don't match messy reality. Tim Wescott shares stories from circuits and communications to show how chasing the theoretical global optimum can waste time and money. He recommends framing 'best' in practical terms, validating models, and optimizing for cost and impact so products ship on time and actually work in the real world.
Feedback Controllers - Making Hardware with Firmware. Part 5. Some FPGA Aspects.
This installment digs into practical FPGA choices and board-level issues for a low-latency, floating-point feedback controller. It compares a Cyclone V implementation against an older SHARC-based design, quantifies the tradeoff between raw DSP resources and cycle latency, and calls out Gotchas found on the BeMicro CV A9 evaluation card. Engineers get concrete prompts for where to optimize: clocking, DSP-block use, I/O standards, and algorithm partitioning.
Design IIR Filters Using Cascaded Biquads
High-order IIR filters are numerically sensitive, especially at low cutoff frequencies. This article shows how to implement a Butterworth lowpass as a cascade of second-order biquads, deriving the per-section coefficient formulas and giving a Matlab biquad_synth example. It explains computing denominator coefficients from pole pairs, using b = [1 2 1] with K = sum(a)/4 for unity DC gain, and highlights reduced quantization sensitivity.
Feedback Controllers - Making Hardware with Firmware. Part 10. DSP/FPGAs Behaving Irrationally
A practical approach to emulating lossy transmission lines in real time, using pole-zero approximations to replace irrational s-domain behaviors and enable FPGA implementation. The author shows 8-pole/zero fits for Zo(s) and a 6-pole/zero plus delay for P(s), validated against LTSpice and MATLAB. Conversion to sampled-data Zo(z) and biquad implementations is detailed, along with issues in single-precision arithmetic and mitigations such as mixed sample rates and partial-fraction decomposition.
An Efficient Linear Interpolation Scheme
A simple trick slashes the cost of linear interpolation to at most one multiply per output sample, and often to none. The post shows a zero-order-hold based network that preserves input samples, has a short L-1 transient, and lets 1/L scaling be implemented as a binary shift when L is a power of two. It also gives a fixed-point layout that moves scaling to the end to reduce quantization distortion.
A poor man's Simulink
Markus Nentwig built a compact glue layer that embeds NGSPICE into Octave to cosimulate continuous-time circuits and digital control. The article walks through an RC lowpass example, the MEX-based Octave interface, and the breakpoint-driven cosimulation flow, showing how adaptive SPICE integration handles asynchronous and time-triggered events. It presents a practical, low-cost alternative to Simulink for tightly coupled analog-digital system design.
Dealing With Fixed Point Fractions
Fixed-point fractional math is easy to botch, and this post lays out pragmatic ways to avoid those mistakes. It clarifies the difference between integer and fractional overflow, shows how Q notation helps track binary-point scaling, and explains why multiplies add sign bits that may require shifting. Read for concrete FPGA strategies: keeping bit growth, selective shifts, or aggressive normalization, plus testing tips.
Canonic Signed Digit (CSD) Representation of Integers
Canonic Signed Digit (CSD) encoding slashes the number of nonzero bits in integer coefficients, enabling multiplierless FIR filters implemented with shifts and adds. This post uses MATLAB code to demonstrate CSD rules, show how negative values work, and plot the distribution of signed digits as bit width changes. It finishes with practical techniques to minimize signed digits per coefficient for area and power efficient filter designs.
Part 11. Using -ve Latency DSP to Cancel Unwanted Delays in Sampled-Data Filters/Controllers
Negative-latency DSP can cancel ADC, FPGA/DSP, DAC and propagation delays to deliver near-zero unwanted latency filtering. Steve Maslen explains how to split a digital filter into a simple feed gain b0 and an advanced DF3 block that produces samples one sample early, then recombine them so sampled-data delays cancel. MATLAB c2d examples, a PID case study and FPGA test-bed results show the technique is practical and proven, with active IP noted.
Matlab Code to Synthesize Multiplierless FIR Filters
Learn how to build multiplierless FIR lowpass filters in Matlab using Canonic Signed-Digit coefficients. The post explains converting Parks-McClellan floating-point taps to scaled integers, then to exact CSD digits, and includes two m-files that search maintap scaling to minimize signed digits while preserving the filter response. Practical notes cover external gain compensation, the 2/3 full-scale CSD limit, and sensitivity to pass/stop edges.
Feedback Controllers - Making Hardware with Firmware. Part 7. Turbo-charged DSP Oscillators
You can extract high-quality, high-sample-rate sine waves from FPGAs even when floating-point units are constrained by latency. This article compares Intel's NCO IP (multiplier option) with floating-point recursive biquads on Cyclone V and Cyclone 10 GX, and explains a boosted-sample-rate technique that pushes performance toward a 48Msps DAC target. Practical measurement results, spectral data, and resource/cost trade-offs are highlighted.
Feedback Controllers - Making Hardware with Firmware. Part 4. Engineering of Evaluation Hardware
Following on from the previous abstract descriptions of an arbitrary circuit emulation application for low-latency feedback controllers, we now come to some aspects in the hardware engineering of an evaluation design from concept to first power-up. In due course a complete specification along with application examples will be maintained on the project website.- Part 1: Introduction
- Part 2:...
