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Discussion Groups | DSP & FPGA | Signal communication betweem process in VHDL

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Signal communication betweem process in VHDL - bing...@meidensg.com.sg - Jul 11 8:20:46 2008



Hi,
I found a strange problem. In the following VHDL code, I want to use a signal named (coming) to
tell another process data is coming.  But I found it did not work.
And if I delete all the case portion in the second process, it works. 

Why? Could anyone give me a hint? Thanks
entity filter is
port(indata:in std_logic_vector(7 downto 0);
     outdata:out std_logic_vector(rank-1 downto 0);  
     en:in std_logic;
     clk_adc:in std_logic;
	  clk_ref:in std_logic;
     add_en:out std_logic;
     rf:in std_logic);
end filter;

architecture beh of filter is

signal coming: std_logic:='0';
signal databuffer: def(rank-1 downto 0);

begin

 process(clk_adc)   --get in data to buffer
variable temp:def(rank-1 downto 0);	--keep the current rank nos of datain temp0 ~ temp9
begin
if(clk_adc'event and clk_adc='1') then
	if(en='1') then
		for i in (rank-1) downto 1 loop
			temp(i):=temp(i-1);
		end loop;
		temp(0):=indata;
		databuffer<=temp;
		coming<='1';		 --- ??????????????????????????????????
	end if;
		
	end if;
end process;
process(clk_ref)
variable tempout:std_logic_vector(rank-1 downto 0);
variable count:unsigned(3 downto 0):="0000";
begin
if (clk_ref'event and clk_ref='1' and coming='1') then 
	add_en<=coming;
	
	count:="0001";
		--case problem????
	case count is
		when "0001"=>for i in rank-1 downto 0  loop    
		              tempout(i):=databuffer(i)(0);       
		              end loop;                     
						  outdata<=tempout;
	                    --if s='1' then  
    		               -- add_en<='1';
        		            --end if;
        when "0010"=>for i in rank-1 downto 0  loop
		              tempout(i):=databuffer(i)(1);
		              end loop;
						   outdata<=tempout;
                      --s:='0';
        when "0011"=>for i in rank-1 downto 0  loop
		              tempout(i):=databuffer(i)(2);
		              end loop;
						   outdata<=tempout;
        when "0100"=>for i in rank-1 downto 0  loop
		              tempout(i):=databuffer(i)(3);
		              end loop;
						   outdata<=tempout;
		when "0101"=>for i in rank-1 downto 0  loop
		              tempout(i):=databuffer(i)(4);
		              end loop;
						   outdata<=tempout;
        when "0110"=>for i in rank-1 downto 0  loop
		              tempout(i):=databuffer(i)(5);
		              end loop;
						   outdata<=tempout;
        when "0111"=>for i in rank-1 downto 0  loop
		              tempout(i):=databuffer(i)(6);
		              end loop;
						   outdata<=tempout;
        when "1000"=>for i in rank-1 downto 0  loop
		              tempout(i):=databuffer(i)(7);					   
		              end loop;
						   outdata<=tempout;
		  when others=>coming<='0';
		 --when others=> if rf='1' then add_en<='0';coming<='0';
		--when others=> add_en<='0';
         --             end if;
	end case;	
	
	----------------------------------------------------

	count:=count+1;

end if;
end process;
end beh; 



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Re: Signal communication betweem process in VHDL - jjma...@yahoo.co.in - Aug 19 21:06:27 2008


hi,

I will use the Blackfin ADSP-BF 548 processor.
I am interfacing the LCD to EPPI port.there is no LCD controller on LCD.
how to start with blackfin ADSP-BF 548 processor.??There is no LCD controller so just send the
data to the port right??
Please give a suggetion.

Regards,
JASMIN



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