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Discussion Groups | DSP & FPGA | VHDL loop error

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VHDL loop error - syya...@yahoo.com - Mar 23 15:02:46 2008



This is a typical counter which counts until 31 with every clock coming in
but im havin this error
[quote]Error (10398): VHDL Process Statement error at count31.vhd(27): Process Statement must
contain only one Wait Statement[/quote]

why can't i have more than more than 1 wait statement in the process, if not how am i ever to
loop it?
any ideas?

[quote]library IEEE;
use  IEEE.STD_LOGIC_1164.all;
use  IEEE.STD_LOGIC_ARITH.all;
use  IEEE.STD_LOGIC_UNSIGNED.all;

entity  COUNT31 is

   port ( CLK: in std_logic;

           COUNT: out integer);

   end COUNT31;

architecture behav_COUNT of COUNT31 is

begin

   P_COUNT: process

     variable intern_value: integer;

	begin
	
  intern_value:=0;
while (intern_value<31) loop

wait until CLK='1';
intern_value:=intern_value + 1;
COUNT <= intern_value;

end loop;

end process P_COUNT;

end behav_COUNT;[/quote]

when i try to change wait [b]until CLK='1';[/b] to [b]if (CLK'event and CLK='1') then[/b]

It gave me warning of exceeding 10,000 iteration.

Why it wont exit the loop when the condition of [b](intern_value<31)[/b] is fulfilled?



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