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Discussion Groups | TMS320C55x | Re: Question: Where is the explicit parallel execution code in the b

Technical discussions about the TI C55x DSPs (including the c5501, c5502, c5503, c5507, c5509, c5510 and OMAP5910).

  

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Re: Question: Where is the explicit parallel execution code in the b - Andrew Nesterov - Mar 18 12:42:07 2008



Hi Jeff,

Very interesting indeed, but I cannot understand one thing, could you help me:

> Subject Re: Question: Where is the explicit parallel execution code in the b
> Posted by: "Jeff Brower" j...@signalogic.com jbrower888
> Date: Mon Mar 17, 2008 8:28 am ((PDT))
>
> > PS: You can have a look at the 12 rules of parallelism
> > in the help files of code composer. Key Word:
> > Parallelism.
>
> Yes I know, I've done a lot of C55x programming.
>
> As I've mentioned, everything you need is encoded in the binary.  Your concerns about
> "implied parallelism", "soft dual parallelism" etc are determined by
the assembler
> (:: symbol put there by the programmer or the asm/compiler) or C code compiler (||
> symbol put there by the programmer or the compiler).  There are no "compare this
> op-code with that one and decide whether to enable parallel operation" type of
> decisions being made by the CPU at run-time.  This is why the C55x Instruction Set
> Reference Guide goes to great lengths to explain the rules -- so you as a programmer
> can follow the rules.

I looked at the opcode map of c55 instructions, some of the opcodes do have
a parallel enable bit, while others do not. The problem for me seem to be in 
that the instructions that do not have an explicit E bit could also be 
exec'ed in parallel; e.g. an implied parallel (two different operations)
instruction does not have the E bit, but still can be executed in parallel
with another instruction, or so I read in the IS manual.

The question I'd like to ask is how does the CPU know this and where is that
something that differentiate a parallel pair from a non-parallel?

I found it a funny explanation of the E bit in the table 6-2 of spru374g :)
which is:
 	0 	Parallel Enable bit is cleared to 0
 	1 	Parallel Enable bit is set to 1
Very informative :)

It is much simplier with the c6000 opcodes, where one easily can say which
instructions are in a single EP, just by looking at the P (0-th) bit in the
opcode.

Thanks and regards,

Andrew
> My suggestion is that you write different combinations of test code and look closely
> at the generated op-codes.  Yes it's tedious and hard work to cover all the
> combinations and look through the bits, but that's your answer.
>
> As CCS has a built-in 55x simulator, why do you need to write your own simulator?  Is
> this a class project?  To offer a low-cost alternative to CCS?  Linux platform?
>
> -Jeff
>

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