Carl-

> The simulator executes the decoded instructions
> serially, but it needs to know if a previous
> instruction, like "repeat" will affect just the next
> instruction or the next two paralleled instructions. I
> need to know in advance when there's present
> parallelism in order to preserve the behaviour of the
> code.
> 
> It's different to execute:
> 
> RPT #3
> MPYM *AR1-, *CDP, AC1 //Only MPYM is repeated 3 times
> XOR AR2, T1
> 
> to:
> RPT #3
> MPYM *AR1-, *CDP, AC1 || XOR AR2, T1 //Both
> instructions are repeated 3 times.
> 
> So what I need to find is how the compiler encodes (if
> it does so) the parallel "operator" if neither of the
> instructions have a parallel bit, but are legally
> parallelizables. For example AADD TAx, TAy with AMOV
> k8, TAz (see Soft Dual parallelism)

I've read through the section on Soft Dual Parallelism in the C55x DSP Mnemonic
Instruction Set Reference Guide, and I'm not understanding your problem.  First, all
such decisions are made at compile-time -- whether any instructions will be executed
in parallel is completely encoded in the binary.  There is no run-time decision.

So what is your issue?  If your simulator reads the binary, then you will *always*
know whether instructions are in parallel or not.  Unless your simulator is also
doing compilation.  Is it?

-Jeff



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Hi Jeff,

The simulator I'm programming knows the opcodes of
each instruction. The decoder I've built reads every
instruction defined on the DSP. I will explain my
doubt with an example.

Suppose there are 3 instructions: "A", "B" and "C".
"A" has a "parallel enable bit" (E bit) but "B" and
"C" don't.
Suppose "A" and ("B" or "C") can be executed in
parallel thanks to the E bit.
But ("B" and "C") can only be parallelized through
Soft dual Parallelism.

So, with my simulator I can detect the E bit and
execute "A" and "C", for example, in parallel.

But if "B" and "C" need to be executed in parallel I
have not an E bit. So, is it there some code, for
example, an special byte (or similar) that tells the
DSP that "B" and "C" can execute in parallel, or I
will have to program the 12 rules of parallelism in
order to identify if two instructions can be executed
in parallel? Check the fields of every instruction,
check for resource conflicts and so on (Yes, I'm a
lazy person that doesn't want to program those rules)

Is it more clear my problem?

Thanks for your time and answer.

Carl. 

PS: You can have a look at the 12 rules of parallelism
in the help files of code composer. Key Word:
Parallelism.

--- Jeff Brower <j...@signalogic.com> escribió:

> Carl-
> 
> > The simulator executes the decoded instructions
> > serially, but it needs to know if a previous
> > instruction, like "repeat" will affect just the
> next
> > instruction or the next two paralleled
> instructions. I
> > need to know in advance when there's present
> > parallelism in order to preserve the behaviour of
> the
> > code.
> > 
> > It's different to execute:
> > 
> > RPT #3
> > MPYM *AR1-, *CDP, AC1 //Only MPYM is repeated 3
> times
> > XOR AR2, T1
> > 
> > to:
> > RPT #3
> > MPYM *AR1-, *CDP, AC1 || XOR AR2, T1 //Both
> > instructions are repeated 3 times.
> > 
> > So what I need to find is how the compiler encodes
> (if
> > it does so) the parallel "operator" if neither of
> the
> > instructions have a parallel bit, but are legally
> > parallelizables. For example AADD TAx, TAy with
> AMOV
> > k8, TAz (see Soft Dual parallelism)
> 
> I've read through the section on Soft Dual
> Parallelism in the C55x DSP Mnemonic
> Instruction Set Reference Guide, and I'm not
> understanding your problem.  First, all
> such decisions are made at compile-time -- whether
> any instructions will be executed
> in parallel is completely encoded in the binary. 
> There is no run-time decision.
> 
> So what is your issue?  If your simulator reads the
> binary, then you will *always*
> know whether instructions are in parallel or not. 
> Unless your simulator is also
> doing compilation.  Is it?
> 
> -Jeff
> 


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