Gary-

> I believe your assumptions are incorrect.  The whole point of "soft-
> parallelism" is to do it at runtime, not compile-time.  This type of
> behavior is often seen in pipelined processors, especially those with
> multiple execution pipelines.

Does TI documentation support your comments?  Is there a specific SPRU-number or
other doc that indicates run-time decisions?

I'm dubious about "intelligent run-time decisions" on 55x devices as those are
relatively old (designed in 2000/2001) and TI hasn't introduced anything dramatically
new for the CPU/core of the 55x line in the last few years, as they've done for C64x
(e.g. C64x+ core).

-Jeff

> --- In c...@yahoogroups.com, bla bla <perro_verde_lunar@...> wrote:
> >
> > Hi,
> >
> > I've read the Instruction Set Reference Guide but my
> > problem it is not how to obtain paralleism on my DSP
> > code, my problem how to handle parallelism in the
> > simulator I am programming. I could program the rules
> > and let my simulator handle parallelism but losing too
> > many MIPS in the process.
> >
> > Parallelism is determined at compile time in C55x, and
> > reading the CPU Reference Guide (SPRU371F), page 1-7,
> > it's clearly written that the instruction decoder
> > "determines whether the CPU has been INSTRUCTED to
> > execute two instructions in parallel", so I assume
> > that somewhere in the binary there are some hints for
> > the soft dual parallelism and other exceptions cases.
> > Maybe the DSP's decoder has a big hardware LUT that
> > automatically tells the DSP to execute the following
> > two instructions in parallel.
> >
> > Thanks for your answer and time.
> >
> > Carl.
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution
for Commercial & Consumer End Equipment: www.ti.com/dm6467

Hi Jeff,

In the CPU reference guide book (SPRU371F), at page
1-7 it's written:

"The instruction decoder:

- identifies instruction boundaries so that it can
decode 8-, 16-, 24-, 32-, 40- and 48-bit instruction.

- DETERMINES WHETHER THE CPU HAS BEEN INSTRUCTED TO
EXECUTE TWO INSTRUCTIONS IN PARALLEL.

- Sends decoded execution commands..."

So, I think that support our point of view. 

Thanks for your answer and time.

Carl.

--- Jeff Brower <j...@signalogic.com> escribió:

> Gary-
> 
> > I believe your assumptions are incorrect.  The
> whole point of "soft-
> > parallelism" is to do it at runtime, not
> compile-time.  This type of
> > behavior is often seen in pipelined processors,
> especially those with
> > multiple execution pipelines.
> 
> Does TI documentation support your comments?  Is
> there a specific SPRU-number or
> other doc that indicates run-time decisions?
> 
> I'm dubious about "intelligent run-time decisions"
> on 55x devices as those are
> relatively old (designed in 2000/2001) and TI hasn't
> introduced anything dramatically
> new for the CPU/core of the 55x line in the last few
> years, as they've done for C64x
> (e.g. C64x+ core).
> 
> -Jeff
> 
> > --- In c...@yahoogroups.com, bla bla
> <perro_verde_lunar@...> wrote:
> > >
> > > Hi,
> > >
> > > I've read the Instruction Set Reference Guide
> but my
> > > problem it is not how to obtain paralleism on my
> DSP
> > > code, my problem how to handle parallelism in
> the
> > > simulator I am programming. I could program the
> rules
> > > and let my simulator handle parallelism but
> losing too
> > > many MIPS in the process.
> > >
> > > Parallelism is determined at compile time in
> C55x, and
> > > reading the CPU Reference Guide (SPRU371F), page
> 1-7,
> > > it's clearly written that the instruction
> decoder
> > > "determines whether the CPU has been INSTRUCTED
> to
> > > execute two instructions in parallel", so I
> assume
> > > that somewhere in the binary there are some
> hints for
> > > the soft dual parallelism and other exceptions
> cases.
> > > Maybe the DSP's decoder has a big hardware LUT
> that
> > > automatically tells the DSP to execute the
> following
> > > two instructions in parallel.
> > >
> > > Thanks for your answer and time.
> > >
> > > Carl.
> 

------------------------------------

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for Commercial & Consumer End Equipment: www.ti.com/dm6467