We have a situation on one of our legacy design of 320C31 DSP. Reset 
pin of C31 is connecting to Maxim Power on Reset chip (MAX708). At 
power up, There is a clock coming in to X2_CLK of C31, but there is no 
divided by two H1 nor H3 clocks coming out. If we force external 
Master Reset to MAX708, to create C31 reset after power up, H1 clock 
will come out. Once the H1 clocks coming out, we are able to erase 
flash, programming it, and upload FPGA firmware through emulator port. 
We never able to see this anomaly again after programming the flash 
and upload FPGA firmware. I like to know what are possible causes of 
this failure. I am greatly appriciated.

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