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Decimation (CIC) filter in VHDL

Hi all, I am currently in the process of designing a decimation filter for a 16bit Sigma Delta ADC. I suspect it will be a CIC filter followed by a FIR filter. I am facing great difficulty understanding such filter, as my experience in usually with analog circuits, and not DSP. My ques...

CIC Compensating filter

I'm designing a CIC filter to perform a hardware efficient downsample. My application is a little bit different in that the downsample factor isn't very large, we're just doing a CIC in order to save multiplies in the FPGA. I'm running into problems with the compensating filter, however. So f...

filters ?

Hello all, i am a student .I have many questions to ask all dsp brains.(definitely basics)kindly reply 1)why should we go for a digital filter in a design,Is there a digital Low pass,high pass ,band pass filters ?if yes,,,pls hint on how they are designed? (VHDL or with statements ) How do we...

Re: CIC filter question

Mark Borgerding wrote: > Jerry Avins wrote: > > > Mark Borgerding wrote: > > > > ... > > > > > > > I don't think a Hogenaur(sp?) representation of a CIC filter is > > > appropriate in floating point. > > > > > > Correct. Even a boxcar averager, in which the oldest sample is > ...

Re: Best tool(s) for filter float->fixed->VHDL flow?

A CIC filter cannot be implemented in floating point. To get it to work it must be done in non-saturating integer math, such as is done using non-saturating two's complement representation. The integer math must wrap around. Dirk A. Bell tom1@launchbird.com (Tom Hawkins) wrote in message...

Re: CIC filters

On Fri, 20 Aug 2004 08:28:38 -0400, Paul Costa wrote: > Hi Robert, > > Here are a few good references for CIC filters: > > Frerking, Marvin E., Digital Signal Processing in Communications > Systems, Kluwer Academic Publishers, 1994. > > Lyons, Richard G., Understanding Digital Sign...

CIC filter

Hi, Can any of you please help me with the question below? Some paper said that CIC filter has a high gain and needed to be compensated? From Mattew P. Donadio: "For a CIC decimator, the normalized gain at the output of the last comb lies in the interval of 1/2 and 1. When R (decimation rati...

CIC filter question (a DC offset at the CIC filter output?)

Dear friends, I am implemeting a CIC filter for a Delta-Sigma ADC, my question is that (assuming the CIC filter has one pair of integrater and comb). Since the input is one bit (0 or 1), the output of the intergrator will always be that the following sample is larger or equal to the previou...

Re: related question Re: Question about computing a "moving variance"

in article sm3h9yth.fsf@ieee.org, Randy Yates at yates@ieee.org wrote on 02/27/2005 21:56: > robert bristow-johnson writes: > > [...] > > but > > > > E{ S^2 } = (N-1)/N * E{ (x[n]-m)^2 } = (N-1)/N * sigma^2 > > How is this derived? oh, it's kinda a bitch. i think ...

CIC filters

Hello, I'm going to implement a decimating CIC filter (inside an FPGA chip), but there are three unclear details. Could you please explain me them? 1. How should I connect integrators (and combs)? The number of accumulator bits (let's call it N) can be easily computed, but how wide should b...

CIC Filter design for multiple FM carrier demod

Hi All, I am working on a project in which we are attempting to demod multiple (analog) FM radio stations in a FPGA. I have been trying to work out how to design the CIC / FIR filter pair in the DDC section of this design. I have a input sampling rate of 80MSPS, which undersamples a clean...

Re: What is moving average?

axlq wrote: > In article , > Ant_Magma wrote: > > > so lets say the moving avg block now contains the avg value of 1~20 > > samples. When then 21st sample enters, the 1st sample that was in the > > moving avg block will be 'popped' out and the new average (2~21) is > > calculated? Or...

CIC Group Delay

I would like to know if I can predict what the group delay of a CIC filter is. I have an agressive FIR BPF where the sample rate is 2000 x the filter bandwidth. The group delay is longer than I would like it to be. Could a CIC filter offer a lower group delay? I'll need to interpolate back ...

RE: Demod Woes

Hi All, This email is partly an update and thanks for past help, and partly a plea for further help. Thanks for your replies from my previous thread on my demod issues, I have had someone send me some fir coeff's for the differentiators which I implemented with no noticable improvement i...

Re: Demod Woes

Hi Dirk, Thanks for your thoughts, I have interdispersed my replies in below. > I have used the I,Q,dI,dQ equation below in a high-performance FM > receiver. It worked really well. See questions below. > > Dirk > > Paul Solomon wrote: > > > Hi All, > > > > This email is...

Re: Which processor for decimation?

Any processor can do this. I would choose one that has a math library available as you may want to use floating point to make the implementation simple. You want a CIC filter followed by halfband compensation filter. Then your final butterworth filter. "Emiliano" wrote in message news...

Re: A filter implemented with 2 accumulators, how does it work?

On Thu, 26 Jan 2006 12:32:43 -0500, Jerry Avins wrote: (snipped) > > > > Is it a correct filter? What is its frequence response? Thank you! > > Brian, > > Asking three times won't get you more answers than asking once. You need > to give more details before anyone can comment ...

Re: DC blocker

robert bristow-johnson wrote: > in my simple life, poles have to be *strictly* stable for me to think of > them as any sort of "stable". that way i don't have to think about whether > any of the poles are compound poles (still strictly stable) or what kind of > finite, bounded input...

poor constellation after CIC filter

I am trying to simulate a rational sample rate conversion architetcure using CIC filters (decimation) and farrow structure (interpolation). Input data is QPSK modulated and upsampled by a large factor (325 to be exact). I try to decimate the signal by 125 in three stages. each stage is in turn a C...

Re: Approach to demodulating AM-signals?

"Mr M" wrote in message news:4408965c$0$15784$14726298@news.sunsite.dk... > Hello > > > > I need to sample and demodulate an AM-signal that is between 30 kHz to 100 > kHz. The signal has a bandwidth of about 10 kHz. > > > > What approach should I use? > > > > I'm th...

Re: What is the relation between sigma-delta ADC's resolution with the CIC's bit growth?

stephenduan4513 wrote: > I've designing a 1bit sigma-delta ADC recently. Some problems are annoying > me so much. > The first one is how I can understand the resolution of such ADC by saying > that they have a 16bit resolution? Anyway,they have only 1bit output. Then > how can I decide w...

Re: Blinded by math. Was "How does an inverter affect phase?"

Jerry Avins wrote: > Wilson wrote: > > > > Yes, but this newsgroup is about Digital Signal Processing, so when you > > perform a multiplication by -1 digitally (in hardware or software), > > that is an inverter and its effect on the signal phase (for all > > frequencies, including D...

Re: Downconverting a baseband signal with NCO of 0MHz

I received a series of additional questions regarding this off-line which I am taking the liberty to bring here so that others can also benefit from my responses: > 1. NCO I am talking is for clock generation made with in the FPGA using > a simple accumulator. It has nothing to do wi...

Re: Large moving average

Steve Underwood wrote: > Mark Borgerding wrote: ... > > Using feedback in the above manner described leads to a potentially > > unstable situation -- a pole on the unit circle. ... > > > Why did you bring such unnecessary complexity into your description? > Looking at poles and zeros ...

Help: Digital Up Convert(DUC) in FPGA.

Hi, I am trying to implement a Nicam modulator in a fpga. The Nicam modulation is a digital sound modulation of analog TV, and use DQPSK. I have some problem when implement the digital up converter(DUC) in fpga. The DUC comprise the cascade of pulse filter, CIC compensation filter CIC fil...

fixed point CIC filter

Hi: Can anyone help me to understand why CIC filter can not be implemented in floating point? Mr. Dirk A Bell mentioned: > > A CIC filter cannot be implemented in floating point. To get it to > > work it must be done in non-saturating integer math, such as is done > > using non-saturating two...

Re: FIR design to filter and decimate concurrently (i.e., w/o buffering)

It is difficult to advice anything since no requirements are set. You may consider a CIC filter. It is basically a cascade of moving average filters implemented in a smart way. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com Mikial Chubarov wrot...

Re: on decimate filters

Hi, For IF DDC converter you can go with CIC filter followed by FIR filter. CIC filter does most of the decimation for you, and for the out-of-band suppression you can go with the FIR filter. CIC filter does not need any multipliers.... You can find lot of materials relating to design of C...

Re: Quadrature tone decoder

patrick.melet@dmradiocom.fr wrote: > My input signal is a frequency multiplex with tone up to 74 kHz, so I > need to sample at 300 kHz to make a NCO with about 4 samples... No problem here: 74kHz will be aliased to 14kHz and fitered out. > And then, in your solution you don't have a...

Re: Unusual Floating-Point Format Remembered?

Jerry Avins wrote: > > > > But is 64 bits enough? No. > > 64 bits provides a range of +/- 9,223,372,036,854,775,807. What is the > ratio of the forces of Brownian motion in room temperature air and of a > major earthquake? > Leave the banal comparisons to the journ...

application of cic filter

Hey guys I have to design cic interpolation filter using system generator.I am trying to find any single application like in wireless area or in audio signal.So can anyone please suggest me? ...

Re: Trying to understand CIC interpolation

On Jul 4, 8:17 am, Krishna wrote: > [snip] > > > 2) The CIC interpolation filter is really intended to be used on > > something that is already oversampled, your test signal is not. > > Consequently, the filter gain giving the desired output signal is not > > the low freq gain of ...

abt designing cic filter

I have to design cic interpoaltion filter for the application of QPSK modulator.Can anyone suggest me how can i go for that? ...

using QPSK modulator

Hey guys, I am designing cic interpolation filter using system genartor.I have gone through xilinx website & try to understand about designing. But still i am confused that how can i implement QPSK modulator like an application of cic filter?can anyone suggest me? or how can i combined qpsk modul...

Re: Regarding DC removal filter.

On Sat, 04 Aug 2007 18:18:11 -0000, robert bristow-johnson wrote: > On Aug 3, 9:09 pm, R.Lyons@_BOGUS_ieee.org (Rick Lyons) wrote: > > > > Hi Marcel, > > I don't understand your DC-removal > > scheme. As far as I know, there's no > > low-computation linear-phase way to > > rem...

Interpolation/FIR/etc... =]

Hi all! Here's a brief description of my application: -> I'm using a Stratix II FPGA to generate data samples and send them to an external DAC. -> Data is generated at rates from 1MSPS to 31.25MSPS. -> I've instantiated an Altera FIR Filter to mask shape this data. This filter also does an ...

my first questions about CIC filter input datatype limit in Matlab

hi everyone, when I use FDATools to design a CIC(cascade integrator comb)filter the input datatype must be signed fix point. but after our sigma delta modulator, the output is in double type. how could I transfer between them in order to use CIC filter in Matlab simulink. forgive me my po...

Re: How do I calculate frequency response of multi-stage CIC interpolation filter?

On Wed, 26 Sep 2007 22:24:29 +0800, "G Iveco" wrote: > Here is the code, two stages differetiator, and two stage integrator. > It's very common but how do I plot the frequency response? > > TIA! > > > d = cos(2*pi*(1:1e3)/1e2); > e = zeros(length(d)*10, 1); > > db = [1 0 -1]; > ...

How do I calculate peak value of output from non-unity CIC filter?

My system uses a CIC interpolation (6X) filter. Binary input is fed thru a rcos matched filter with OVS=10, passband BW is B, resulting in data D1, which is subsequently interpolated by CIC to 6X times. The amplitude of interpolated output (D2) is lower than matched filter output, which ca...

Re: CIC filter payoff

kungcoccos wrote: > > On Nov 12, 4:08 pm, "kungcoccos" wrote: > > > Hello everyone! > > > > > > Im in the middle of my thesis and one of the objects that the company > want > > > to know is: > > > > > > When will a implementation of a CIC filter payoff? After some time > > > spe...